From f4184358198b6e08070339b851f28164817bc6ea Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 1 Mar 2006 04:57:39 +0000 Subject: [PATCH] Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll. llvm-svn: 26445 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 40 +++++++++++++++++++++ llvm/lib/Target/PowerPC/PPCISelLowering.h | 2 ++ llvm/lib/Target/PowerPC/README.txt | 25 ------------- 3 files changed, 42 insertions(+), 25 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 204a45a4f9dc..40095223b53a 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -185,6 +185,9 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) setSetCCResultContents(ZeroOrOneSetCCResult); setStackPointerRegisterToSaveRestore(PPC::R1); + // We have target-specific dag combine patterns for the following nodes: + setTargetDAGCombine(ISD::SINT_TO_FP); + computeRegisterProperties(); } @@ -997,6 +1000,43 @@ PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, return BB; } +SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, + DAGCombinerInfo &DCI) const { + TargetMachine &TM = getTargetMachine(); + SelectionDAG &DAG = DCI.DAG; + switch (N->getOpcode()) { + default: break; + case ISD::SINT_TO_FP: + if (TM.getSubtarget().is64Bit()) { + // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. + // We allow the src/dst to be either f32/f64, but force the intermediate + // type to be i64. + if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT && + N->getOperand(0).getValueType() == MVT::i64) { + + SDOperand Val = N->getOperand(0).getOperand(0); + if (Val.getValueType() == MVT::f32) { + Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); + DCI.AddToWorklist(Val.Val); + } + + Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); + DCI.AddToWorklist(Val.Val); + Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); + DCI.AddToWorklist(Val.Val); + if (N->getValueType(0) == MVT::f32) { + Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); + DCI.AddToWorklist(Val.Val); + } + return Val; + } + } + break; + } + + return SDOperand(); +} + /// getConstraintType - Given a constraint letter, return the type of /// constraint it is for this target. PPCTargetLowering::ConstraintType diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index 86264aec38b7..8825b1ef00c6 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -81,6 +81,8 @@ namespace llvm { /// virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); + virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; + /// LowerArguments - This hook must be implemented to indicate how we should /// lower the arguments for the specified function, into the specified DAG. virtual std::vector diff --git a/llvm/lib/Target/PowerPC/README.txt b/llvm/lib/Target/PowerPC/README.txt index 0a119155fef9..b59122f00e4d 100644 --- a/llvm/lib/Target/PowerPC/README.txt +++ b/llvm/lib/Target/PowerPC/README.txt @@ -328,31 +328,6 @@ computable using the spiffy altivec instructions. Compile this: -double %test(double %X) { - %Y = cast double %X to long - %Z = cast long %Y to double - ret double %Z -} - -to this: - -_test: - fctidz f0, f1 - stfd f0, -8(r1) - lwz r2, -4(r1) - lwz r3, -8(r1) - stw r2, -12(r1) - stw r3, -16(r1) - lfd f0, -16(r1) - fcfid f1, f0 - blr - -without the lwz/stw's. - -===-------------------------------------------------------------------------=== - -Compile this: - int foo(int a) { int b = (a < 8); if (b) {