Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.
llvm-svn: 77329
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@ -715,9 +715,18 @@ defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
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defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
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def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
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"mov", " $dst, $src, rrx",
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"rrx", " $dst, $src",
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[(set GPR:$dst, (ARMrrx GPR:$src))]>;
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let Defs = [CPSR] in {
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def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src),
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"lsrs.w $dst, $src, #1",
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[(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
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def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src),
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"asrs.w $dst, $src, #1",
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[(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
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}
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//===----------------------------------------------------------------------===//
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// Bitwise Instructions.
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//
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@ -0,0 +1,19 @@
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2
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define i1 @test1(i64 %poscnt, i32 %work) {
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entry:
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; CHECK: rrx r0, r0
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; CHECK: lsrs.w r1, r1, #1
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%0 = lshr i64 %poscnt, 1
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%1 = icmp eq i64 %0, 0
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ret i1 %1
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}
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define i1 @test2(i64 %poscnt, i32 %work) {
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entry:
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; CHECK: rrx r0, r0
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; CHECK: asrs.w r1, r1, #1
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%0 = ashr i64 %poscnt, 1
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%1 = icmp eq i64 %0, 0
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ret i1 %1
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}
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