From e82862e24ef882dacef845d4f41ab0cdeedc5be9 Mon Sep 17 00:00:00 2001
From: David Goodwin <david_goodwin@apple.com>
Date: Tue, 28 Jul 2009 17:06:49 +0000
Subject: [PATCH] Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.

llvm-svn: 77329
---
 llvm/lib/Target/ARM/ARMInstrThumb2.td   | 11 ++++++++++-
 llvm/test/CodeGen/Thumb2/thumb2-lsr3.ll | 19 +++++++++++++++++++
 2 files changed, 29 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/Thumb2/thumb2-lsr3.ll

diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 1126be44220a..2affa6389c6e 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -715,9 +715,18 @@ defm t2ASR  : T2I_sh_ir<"asr", BinOpFrag<(sra  node:$LHS, node:$RHS)>>;
 defm t2ROR  : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
 
 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
-                   "mov", " $dst, $src, rrx",
+                   "rrx", " $dst, $src",
                    [(set GPR:$dst, (ARMrrx GPR:$src))]>;
 
+let Defs = [CPSR] in {
+def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src),
+                         "lsrs.w $dst, $src, #1",
+                         [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
+def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src),
+                         "asrs.w $dst, $src, #1",
+                         [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
+}
+
 //===----------------------------------------------------------------------===//
 //  Bitwise Instructions.
 //
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-lsr3.ll b/llvm/test/CodeGen/Thumb2/thumb2-lsr3.ll
new file mode 100644
index 000000000000..9bc4b5b7c511
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/thumb2-lsr3.ll
@@ -0,0 +1,19 @@
+; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2
+
+define i1 @test1(i64 %poscnt, i32 %work) {
+entry:
+; CHECK: rrx r0, r0
+; CHECK: lsrs.w r1, r1, #1
+	%0 = lshr i64 %poscnt, 1
+	%1 = icmp eq i64 %0, 0
+	ret i1 %1
+}
+
+define i1 @test2(i64 %poscnt, i32 %work) {
+entry:
+; CHECK: rrx r0, r0
+; CHECK: asrs.w r1, r1, #1
+	%0 = ashr i64 %poscnt, 1
+	%1 = icmp eq i64 %0, 0
+	ret i1 %1
+}