CellSPU: Custom lower truncating stores of i8 to i1 (should not have been
promote), fix signed conversion of indexed offsets. llvm-svn: 59707
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@ -189,9 +189,10 @@ namespace {
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assert(MO.isImm() &&
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assert(MO.isImm() &&
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"printMemRegImmS10 first operand is not immedate");
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"printMemRegImmS10 first operand is not immedate");
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int64_t value = int64_t(MI->getOperand(OpNo).getImm());
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int64_t value = int64_t(MI->getOperand(OpNo).getImm());
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assert((value >= -(1 << (9+4)) && value <= (1 << (9+4)) - 1)
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int16_t value16 = int16_t(value);
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assert((value16 >= -(1 << (9+4)) && value16 <= (1 << (9+4)) - 1)
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&& "Invalid dform s10 offset argument");
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&& "Invalid dform s10 offset argument");
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O << value << "(";
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O << value16 << "(";
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printOperand(MI, OpNo+1);
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printOperand(MI, OpNo+1);
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O << ")";
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O << ")";
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}
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}
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@ -134,7 +134,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setTruncStoreAction(MVT::i8, MVT::i1, Promote);
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setTruncStoreAction(MVT::i8, MVT::i1, Custom);
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setTruncStoreAction(MVT::i16, MVT::i1, Custom);
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setTruncStoreAction(MVT::i16, MVT::i1, Custom);
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setTruncStoreAction(MVT::i32, MVT::i1, Custom);
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setTruncStoreAction(MVT::i32, MVT::i1, Custom);
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setTruncStoreAction(MVT::i64, MVT::i1, Custom);
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setTruncStoreAction(MVT::i64, MVT::i1, Custom);
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