From a7521ee3df1c8b00eb86d546557d3f10e16771e4 Mon Sep 17 00:00:00 2001 From: Scott Michel Date: Thu, 20 Nov 2008 05:01:09 +0000 Subject: [PATCH] CellSPU: Custom lower truncating stores of i8 to i1 (should not have been promote), fix signed conversion of indexed offsets. llvm-svn: 59707 --- llvm/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp | 5 +++-- llvm/lib/Target/CellSPU/SPUISelLowering.cpp | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp b/llvm/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp index 2fdac3376cc6..3037ba30fa3b 100644 --- a/llvm/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp +++ b/llvm/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp @@ -189,9 +189,10 @@ namespace { assert(MO.isImm() && "printMemRegImmS10 first operand is not immedate"); int64_t value = int64_t(MI->getOperand(OpNo).getImm()); - assert((value >= -(1 << (9+4)) && value <= (1 << (9+4)) - 1) + int16_t value16 = int16_t(value); + assert((value16 >= -(1 << (9+4)) && value16 <= (1 << (9+4)) - 1) && "Invalid dform s10 offset argument"); - O << value << "("; + O << value16 << "("; printOperand(MI, OpNo+1); O << ")"; } diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp index 002ef3f66126..1ed3bab733bb 100644 --- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp @@ -134,7 +134,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); - setTruncStoreAction(MVT::i8, MVT::i1, Promote); + setTruncStoreAction(MVT::i8, MVT::i1, Custom); setTruncStoreAction(MVT::i16, MVT::i1, Custom); setTruncStoreAction(MVT::i32, MVT::i1, Custom); setTruncStoreAction(MVT::i64, MVT::i1, Custom);