parent
82e5e1e564
commit
a65e6b8335
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@ -937,9 +937,6 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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Op.getOperand(1),
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Op.getOperand(2),
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Op.getOperand(3));
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case AMDGPUIntrinsic::AMDGPU_brev: // Legacy name
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return DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(1));
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}
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}
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@ -30,9 +30,6 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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// Deprecated in favor of llvm.bitreverse
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def int_AMDGPU_brev : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
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// Deprecated in favor of llvm.amdgcn.s.barrier
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def int_AMDGPU_barrier_local : Intrinsic<[], [], [IntrConvergent]>;
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def int_AMDGPU_barrier_global : Intrinsic<[], [], [IntrConvergent]>;
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@ -11,8 +11,6 @@ declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) #1
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declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>) #1
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declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) #1
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declare i32 @llvm.AMDGPU.brev(i32) #1
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; FUNC-LABEL: {{^}}s_brev_i16:
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; SI: s_brev_b32
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define void @s_brev_i16(i16 addrspace(1)* noalias %out, i16 %val) #0 {
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@ -103,13 +101,5 @@ define void @v_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrsp
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ret void
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}
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; FUNC-LABEL: {{^}}legacy_s_brev_i32:
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; SI: s_brev_b32
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define void @legacy_s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
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%brev = call i32 @llvm.AMDGPU.brev(i32 %val) #1
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store i32 %brev, i32 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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