From a65e6b8335283d6e5aafc358e7e6b97445c928e9 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 15 Jul 2016 21:27:13 +0000 Subject: [PATCH] AMDGPU: Remove brev intrinsic llvm-svn: 275620 --- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 3 --- llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td | 3 --- llvm/test/CodeGen/AMDGPU/bitreverse.ll | 10 ---------- 3 files changed, 16 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 0188724af979..352423ed3ad6 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -937,9 +937,6 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); - - case AMDGPUIntrinsic::AMDGPU_brev: // Legacy name - return DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(1)); } } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td b/llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td index 8c6c3daf408a..a011a85d46aa 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td @@ -30,9 +30,6 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in { [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem] >; - // Deprecated in favor of llvm.bitreverse - def int_AMDGPU_brev : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; - // Deprecated in favor of llvm.amdgcn.s.barrier def int_AMDGPU_barrier_local : Intrinsic<[], [], [IntrConvergent]>; def int_AMDGPU_barrier_global : Intrinsic<[], [], [IntrConvergent]>; diff --git a/llvm/test/CodeGen/AMDGPU/bitreverse.ll b/llvm/test/CodeGen/AMDGPU/bitreverse.ll index 0ef7d5184c1f..62e7904f4382 100644 --- a/llvm/test/CodeGen/AMDGPU/bitreverse.ll +++ b/llvm/test/CodeGen/AMDGPU/bitreverse.ll @@ -11,8 +11,6 @@ declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) #1 declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>) #1 declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) #1 -declare i32 @llvm.AMDGPU.brev(i32) #1 - ; FUNC-LABEL: {{^}}s_brev_i16: ; SI: s_brev_b32 define void @s_brev_i16(i16 addrspace(1)* noalias %out, i16 %val) #0 { @@ -103,13 +101,5 @@ define void @v_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrsp ret void } -; FUNC-LABEL: {{^}}legacy_s_brev_i32: -; SI: s_brev_b32 -define void @legacy_s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { - %brev = call i32 @llvm.AMDGPU.brev(i32 %val) #1 - store i32 %brev, i32 addrspace(1)* %out - ret void -} - attributes #0 = { nounwind } attributes #1 = { nounwind readnone }