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Simplify definition of FP move instructions. 

llvm-svn: 141476
This commit is contained in:
Akira Hatanaka 2011-10-08 03:50:18 +00:00
parent 2365f90676
commit 6be7d6c976
2 changed files with 6 additions and 5 deletions
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9
llvm/lib/Target/Mips/MipsInstrFPU.td
View File

@ -163,10 +163,11 @@ let fd = 0 in {
[(set FGR32:$fs, (bitconvert CPURegs:$rt))]>; [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>;
} }
def FMOV_S32 : FFR<0x11, 0b000110, 0x0, (outs FGR32:$fd), (ins FGR32:$fs), def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>;
"mov.s\t$fd, $fs", []>; def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>,
def FMOV_D32 : FFR<0x11, 0b000110, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs), Requires<[NotFP64bit]>;
"mov.d\t$fd, $fs", []>; def FMOV_D64 : FFR1<0x6, 17, "mov", "d", FGR64, FGR64>,
Requires<[IsFP64bit]>;
/// Floating Point Memory Instructions /// Floating Point Memory Instructions
let Predicates = [IsNotSingleFloat] in { let Predicates = [IsNotSingleFloat] in {

2
llvm/lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -119,7 +119,7 @@ copyPhysReg(MachineBasicBlock &MBB,
Opc = Mips::MTLO, DestReg = 0; Opc = Mips::MTLO, DestReg = 0;
} }
else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
Opc = Mips::FMOV_S32; Opc = Mips::FMOV_S;
else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
Opc = Mips::FMOV_D32; Opc = Mips::FMOV_D32;
else if (Mips::CCRRegClass.contains(DestReg, SrcReg)) else if (Mips::CCRRegClass.contains(DestReg, SrcReg))