Define classes and multiclasses for FP binary instructions.
llvm-svn: 141475
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@ -98,18 +98,13 @@ multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> {
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Requires<[IsFP64bit]>;
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}
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multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp, bit isComm = 0> {
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multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode, bit isComm = 0> {
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let isCommutable = isComm in {
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def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
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(ins FGR32:$fs, FGR32:$ft),
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!strconcat(asmstr, ".s\t$fd, $fs, $ft"),
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[(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>;
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def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
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(ins AFGR64:$fs, AFGR64:$ft),
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!strconcat(asmstr, ".d\t$fd, $fs, $ft"),
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[(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>,
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Requires<[NotFP64bit]>;
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def _S : FFR2P<funct, 16, opstr, "s", FGR32, OpNode>;
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def _D32 : FFR2P<funct, 17, opstr, "d", AFGR64, OpNode>,
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Requires<[NotFP64bit]>;
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def _D64 : FFR2P<funct, 17, opstr, "d", FGR64, OpNode>,
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Requires<[IsFP64bit]>;
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}
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}
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@ -189,10 +184,10 @@ def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr),
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"swc1\t$ft, $addr", [(store FGR32:$ft, addr:$addr)]>;
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/// Floating-point Aritmetic
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defm FADD : FFR1_4<0x10, "add", fadd, 1>;
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defm FDIV : FFR1_4<0x03, "div", fdiv>;
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defm FMUL : FFR1_4<0x02, "mul", fmul, 1>;
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defm FSUB : FFR1_4<0x01, "sub", fsub>;
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defm FADD : FFR2P_M<0x10, "add", fadd, 1>;
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defm FDIV : FFR2P_M<0x03, "div", fdiv>;
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defm FMUL : FFR2P_M<0x02, "mul", fmul, 1>;
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defm FSUB : FFR2P_M<0x01, "sub", fsub>;
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//===----------------------------------------------------------------------===//
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// Floating Point Branch Codes
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@ -245,3 +245,8 @@ class FFR1P<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
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let ft = 0;
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}
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class FFR2P<bits<6> funct, bits<5> fmt, string opstr,
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string fmtstr, RegisterClass RC, SDNode OpNode> :
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FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft),
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!strconcat(opstr, ".", fmtstr, "\t$fd, $fs, $ft"),
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[(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>;
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