Don't bother doing latency calculations in the "fast" scheduler.
llvm-svn: 59461
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9b3bbe9db7
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@ -139,12 +139,6 @@ void ScheduleDAGFast::Schedule() {
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/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
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void ScheduleDAGFast::ReleasePred(SUnit *PredSU, bool isChain,
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unsigned CurCycle) {
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// FIXME: the distance between two nodes is not always == the predecessor's
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// latency. For example, the reader can very well read the register written
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// by the predecessor later than the issue cycle. It also depends on the
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// interrupt model (drain vs. freeze).
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PredSU->CycleBound = std::max(PredSU->CycleBound, CurCycle + PredSU->Latency);
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--PredSU->NumSuccsLeft;
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#ifndef NDEBUG
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@ -277,7 +271,6 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {
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// FIXME: Calculate height / depth and propagate the changes?
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NewSU->Depth = SU->Depth;
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NewSU->Height = SU->Height;
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ComputeLatency(NewSU);
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// LoadNode may already exist. This can happen when there is another
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// load from the same location and producing the same type of value
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@ -293,7 +286,6 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {
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LoadSU->Depth = SU->Depth;
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LoadSU->Height = SU->Height;
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ComputeLatency(LoadSU);
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}
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SUnit *ChainPred = NULL;
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@ -530,13 +522,11 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
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LRegsMap.clear();
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SUnit *CurSU = AvailableQueue.pop();
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while (CurSU) {
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if (CurSU->CycleBound <= CurCycle) {
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SmallVector<unsigned, 4> LRegs;
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if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
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break;
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Delayed = true;
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LRegsMap.insert(std::make_pair(CurSU, LRegs));
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}
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SmallVector<unsigned, 4> LRegs;
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if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
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break;
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Delayed = true;
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LRegsMap.insert(std::make_pair(CurSU, LRegs));
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CurSU->isPending = true; // This SU is not in AvailableQueue right now.
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NotReady.push_back(CurSU);
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