32 lines
1.4 KiB
Markdown
32 lines
1.4 KiB
Markdown
<!-- Provide a brief description of the PR, if the title is insufficient -->
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#### Related PRs / Issues
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<!-- List any related issues here -->
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#### UI / API Impact
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<!-- Roughly, how would this affect the current API or user-facing interfaces? (extend, deprecate, remove, or break) -->
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<!-- Of note: manager config.ini interface, targetutils & bridge scala API, platform config behavior -->
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#### Verilog / AGFI Compatability
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<!-- Does this change the generated Verilog or the simulator memory map of the default targets? -->
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### Contributor Checklist
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- [ ] Did you add Scaladoc to every public function/method?
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- [ ] Did you add at least one test demonstrating the PR?
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- [ ] Did you delete any extraneous prints/debugging code?
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- [ ] Did you state the UI / API impact?
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- [ ] Did you specify the Verilog / AGFI compatability impact?
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<!-- Do this if this PR changes verilog or breaks the default AGFIs -->
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- [ ] (If applicable) Did you regenerate and publicly share default AGFIs?
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<!-- Do this if this PR is a bugfix that should be applied to master -->
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- [ ] (If applicable) Did you mark the PR as "Please Backport"?
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- [ ] (On merge) Did you update release notes in the dev-to-master PR ?
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### Reviewer Checklist (only modified by reviewer)
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- [ ] Did you mark the proper milestone (1.12.0, 1.13.0) ?
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- [ ] Did you check whether all relevant Contributor checkboxes have been checked?
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