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Use midas Chisel generator instead of Chipyard generator

This commit is contained in:
abejgonzalez 2023-08-31 16:01:47 -07:00
parent 0790d378f8
commit fb01ec07b7
3 changed files with 3 additions and 3 deletions
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2
sim/src/main/makefrag/bridges/build.mk
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@ -4,7 +4,7 @@ vcs_args = +vcs+initreg+0 +vcs+initmem+0
$(FIRRTL_FILE) $(ANNO_FILE): $(TARGET_CP) $(FIRRTL_FILE) $(ANNO_FILE): $(TARGET_CP)
@mkdir -p $(@D) @mkdir -p $(@D)
$(call run_jar_scala_main,$(TARGET_CP),chipyard.Generator,\ $(call run_jar_scala_main,$(TARGET_CP),midas.chiselstage.Generator,\
--target-dir $(GENERATED_DIR) \ --target-dir $(GENERATED_DIR) \
--name $(long_name) \ --name $(long_name) \
--top-module $(DESIGN_PACKAGE).$(DESIGN) \ --top-module $(DESIGN_PACKAGE).$(DESIGN) \

2
sim/src/main/makefrag/fasedtests/build.mk
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@ -2,7 +2,7 @@
$(FIRRTL_FILE) $(ANNO_FILE): $(TARGET_CP) $(FIRRTL_FILE) $(ANNO_FILE): $(TARGET_CP)
@mkdir -p $(@D) @mkdir -p $(@D)
$(call run_jar_scala_main,$(TARGET_CP),chipyard.Generator,\ $(call run_jar_scala_main,$(TARGET_CP),midas.chiselstage.Generator,\
--target-dir $(GENERATED_DIR) \ --target-dir $(GENERATED_DIR) \
--name $(long_name) \ --name $(long_name) \
--top-module $(DESIGN_PACKAGE).$(DESIGN) \ --top-module $(DESIGN_PACKAGE).$(DESIGN) \

2
sim/src/main/makefrag/midasexamples/build.mk
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@ -2,7 +2,7 @@
$(FIRRTL_FILE) $(ANNO_FILE): $(TARGET_CP) $(FIRRTL_FILE) $(ANNO_FILE): $(TARGET_CP)
@mkdir -p $(@D) @mkdir -p $(@D)
$(call run_jar_scala_main,$(TARGET_CP),chipyard.Generator,\ $(call run_jar_scala_main,$(TARGET_CP),midas.chiselstage.Generator,\
--target-dir $(GENERATED_DIR) \ --target-dir $(GENERATED_DIR) \
--name $(long_name) \ --name $(long_name) \
--top-module $(DESIGN_PACKAGE).$(DESIGN) \ --top-module $(DESIGN_PACKAGE).$(DESIGN) \