From fb01ec07b7fd2b9090a53f1620b56268a263e47d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 31 Aug 2023 16:01:47 -0700 Subject: [PATCH] Use midas Chisel generator instead of Chipyard generator --- sim/src/main/makefrag/bridges/build.mk | 2 +- sim/src/main/makefrag/fasedtests/build.mk | 2 +- sim/src/main/makefrag/midasexamples/build.mk | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/sim/src/main/makefrag/bridges/build.mk b/sim/src/main/makefrag/bridges/build.mk index 5c8fe7d2..f8bd6fe4 100644 --- a/sim/src/main/makefrag/bridges/build.mk +++ b/sim/src/main/makefrag/bridges/build.mk @@ -4,7 +4,7 @@ vcs_args = +vcs+initreg+0 +vcs+initmem+0 $(FIRRTL_FILE) $(ANNO_FILE): $(TARGET_CP) @mkdir -p $(@D) - $(call run_jar_scala_main,$(TARGET_CP),chipyard.Generator,\ + $(call run_jar_scala_main,$(TARGET_CP),midas.chiselstage.Generator,\ --target-dir $(GENERATED_DIR) \ --name $(long_name) \ --top-module $(DESIGN_PACKAGE).$(DESIGN) \ diff --git a/sim/src/main/makefrag/fasedtests/build.mk b/sim/src/main/makefrag/fasedtests/build.mk index c78a5785..33f39e55 100644 --- a/sim/src/main/makefrag/fasedtests/build.mk +++ b/sim/src/main/makefrag/fasedtests/build.mk @@ -2,7 +2,7 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(TARGET_CP) @mkdir -p $(@D) - $(call run_jar_scala_main,$(TARGET_CP),chipyard.Generator,\ + $(call run_jar_scala_main,$(TARGET_CP),midas.chiselstage.Generator,\ --target-dir $(GENERATED_DIR) \ --name $(long_name) \ --top-module $(DESIGN_PACKAGE).$(DESIGN) \ diff --git a/sim/src/main/makefrag/midasexamples/build.mk b/sim/src/main/makefrag/midasexamples/build.mk index c78a5785..33f39e55 100644 --- a/sim/src/main/makefrag/midasexamples/build.mk +++ b/sim/src/main/makefrag/midasexamples/build.mk @@ -2,7 +2,7 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(TARGET_CP) @mkdir -p $(@D) - $(call run_jar_scala_main,$(TARGET_CP),chipyard.Generator,\ + $(call run_jar_scala_main,$(TARGET_CP),midas.chiselstage.Generator,\ --target-dir $(GENERATED_DIR) \ --name $(long_name) \ --top-module $(DESIGN_PACKAGE).$(DESIGN) \