Merge pull request #197 from firesim/print-synthesis
Enable Endpointed Print synthesis
This commit is contained in:
David Biancolin
GitHub
commit
5be11e3861
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@ -10,31 +10,32 @@
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# own images.
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[fireboom-singlecore-nic-ddr3-llc4mb]
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agfi=agfi-05c7620b62b901690
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agfi=agfi-00857d0de5aa1d7b7
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deploytripletoverride=None
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customruntimeconfig=None
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[fireboom-singlecore-no-nic-ddr3-llc4mb]
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agfi=agfi-07f3c2762e4349327
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agfi=agfi-0659b86373011fe04
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deploytripletoverride=None
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customruntimeconfig=None
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[firesim-quadcore-nic-ddr3-llc4mb]
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agfi=agfi-0c078780eadb4203b
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agfi=agfi-0b929d88d9f66c9f5
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deploytripletoverride=None
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customruntimeconfig=None
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[firesim-quadcore-no-nic-ddr3-llc4mb]
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agfi=agfi-0e9945a181069cc67
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agfi=agfi-0fb7f0fe1602f9cd9
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deploytripletoverride=None
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customruntimeconfig=None
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[firesim-singlecore-no-nic-lbp]
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agfi=agfi-05ca0d174e131e124
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agfi=agfi-047644ef3f61ae041
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deploytripletoverride=None
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customruntimeconfig=None
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[firesim-supernode-quadcore-nic-ddr3-llc4mb]
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agfi=agfi-012e0df3c4b90375d
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[firesim-supernode-singlecore-nic-lbp]
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agfi=agfi-0498cf07932fd2e99
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deploytripletoverride=None
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customruntimeconfig=None
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@ -12,3 +12,4 @@ This section describes methods of debugging the target design and the simulation
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Debugging-Hardware-Using-ILA.rst
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TracerV.rst
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DESSERT.rst
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printf-synthesis.rst
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@ -0,0 +1,66 @@
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Printf Synthesis
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===================
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MIDAS can synthesize printfs present in FIRRTL (implemented as ``printf``
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statements) that would otherwise be lost in the FPGA synthesis flow. Rocket and
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BOOM have printfs of their commit logs and other useful transaction
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streams.
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::
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C0: 409 [1] pc=[008000004c] W[r10=0000000000000000][1] R[r 0=0000000000000000] R[r20=0000000000000003] inst=[f1402573] csrr a0, mhartid
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C0: 410 [0] pc=[008000004c] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r20=0000000000000003] inst=[f1402573] csrr a0, mhartid
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C0: 411 [0] pc=[008000004c] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r20=0000000000000003] inst=[f1402573] csrr a0, mhartid
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C0: 412 [1] pc=[0080000050] W[r 0=0000000000000000][0] R[r10=0000000000000000] R[r 0=0000000000000000] inst=[00051063] bnez a0, pc + 0
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C0: 413 [1] pc=[0080000054] W[r 5=0000000080000054][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[00000297] auipc t0, 0x0
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C0: 414 [1] pc=[0080000058] W[r 5=0000000080000064][1] R[r 5=0000000080000054] R[r16=0000000000000003] inst=[01028293] addi t0, t0, 16
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C0: 415 [1] pc=[008000005c] W[r 0=0000000000010000][1] R[r 5=0000000080000064] R[r 5=0000000080000064] inst=[30529073] csrw mtvec, t0
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Synthesizing these printfs lets you capture the same logs on a running FireSim instance.
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Enabling Printf Synthesis
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----------------------------
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To synthesize a printf, in your Chisel source you need to annotate the specific
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printfs you'd like to capture. Presently, due to a limitation in Chisel and
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FIRRTL's annotation system, you need to annotate the arguments to the printf, not the printf itself,
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like so:
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::
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printf(midas.targetutils.SynthesizePrintf("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata))
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Be judicious, as synthesizing many, frequently active printfs, will slow down your simulator.
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Once your printfs have been annotated, to enable printf synthesis add the ``WithPrintfSynthesis`` Config to your
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PLATFORM_CONFIG in SimConfigs.scala. During compilation, MIDAS will print the
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number of printfs it's synthesized. In the target's generated header
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(``<DESIGN>-const.h``), you'll find metadata for each of the printfs MIDAS synthesized.
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This is passed as argument to the constructor of the ``synthesized_prints_t``
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endpoint driver, which will be automatically instantiated in FireSim driver.
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Runtime Arguments
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-----------------
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**+printfile**
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Specifies the file into which the synthesized printf log should written.
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**+print-start**
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Specifies the target-cycle at which the printf trace should be captured in the
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simulator. Since capturing high-bandwidth printf traces will slow down
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simulation, this allows the user to reach the region-of-interest at full simulation speed.
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**+print-end**
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Specifies the target cycle at which to stop pulling the synthesized print
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trace from the simulator.
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**+print-human-readable**
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By default, a captured printf trace will be written to file as a raw,
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unformatted binary, as properly formatting the printf further slows the
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simulator. Setting this will properly format the print data before writing
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it to file.
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Related Publications
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--------------------
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Printf synthesis was first presented in our FPL2018 paper, `DESSERT
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<https://people.eecs.berkeley.edu/~biancolin/papers/dessert-fpl18.pdf>`_.
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@ -1 +1 @@
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Subproject commit 50d4a55873741d01f9381f6fa56aa6ced2a4bb5b
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Subproject commit 71a361090c98b89455deb5fd90eba8f08b3b34e8
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@ -23,12 +23,13 @@ SBT_FLAGS ?= -J-Xmx16G -J-Xss8M -J-XX:MaxPermSize=256M -J-XX:MaxMetaspaceSize=51
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firesim_base_dir := $(abspath .)
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# Manage the FIRRTL dependency manually
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FIRRTL_JAR ?= $(firesim_base_dir)/lib/firrtl.jar
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FIRRTL_SUBMODULE_DIR ?= $(firesim_base_dir)/firrtl
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FIRRTL_JAR ?= $(FIRRTL_SUBMODULE_DIR)/utils/bin/firrtl.jar
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$(FIRRTL_JAR): $(shell find $(FIRRTL_SUBMODULE_DIR)/src/main/scala -iname "*.scala")
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$(MAKE) -C $(FIRRTL_SUBMODULE_DIR) SBT="$(SBT) $(SBT_FLAGS)" root_dir=$(FIRRTL_SUBMODULE_DIR) build-scala
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mkdir -p $(@D)
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cp -p $(FIRRTL_SUBMODULE_DIR)/utils/bin/firrtl.jar $(FIRRTL_JAR)
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touch $(FIRRTL_JAR)
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mkdir -p $(firesim_base_dir)/lib
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cp -p $(FIRRTL_JAR) $(firesim_base_dir)/lib/
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firrtl: $(FIRRTL_JAR)
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.PHONY: firrtl
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@ -1 +1 @@
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Subproject commit ba12915e9b93685107c503b3f91b96d491c48459
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Subproject commit 380c233b43c2de53b0ee15a39e9364d438066b9f
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@ -1 +1 @@
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Subproject commit d9251aea8bc7c4f65ea46013e319d41cbdeb1944
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Subproject commit 12991c628ce506cf462e5c5c24688bd99c5b2b74
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@ -11,6 +11,7 @@
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#include "endpoints/sim_mem.h"
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#include "endpoints/fpga_memory_model.h"
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#include "endpoints/synthesized_assertions.h"
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#include "endpoints/synthesized_prints.h"
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firesim_top_t::firesim_top_t(int argc, char** argv)
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{
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@ -333,11 +334,30 @@ uint64_t host_mem_offset = -0x80000000LL;
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#endif
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#endif
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// add more endpoints here
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// There can only be one instance of assert and print widgets as their IO is
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// uniquely generated by a FIRRTL transform
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#ifdef ASSERTIONWIDGET_struct_guard
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#ifdef ASSERTIONWIDGET_0_PRESENT
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ASSERTIONWIDGET_0_substruct_create;
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endpoints.push_back(new synthesized_assertions_t(this, ASSERTIONWIDGET_0_substruct));
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add_endpoint(new synthesized_assertions_t(this, ASSERTIONWIDGET_0_substruct));
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#endif
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#endif
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#ifdef PRINTWIDGET_struct_guard
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#ifdef PRINTWIDGET_0_PRESENT
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PRINTWIDGET_0_substruct_create;
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print_endpoint = new synthesized_prints_t(this,
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args,
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PRINTWIDGET_0_substruct,
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PRINTWIDGET_0_print_count,
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PRINTWIDGET_0_token_bytes,
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PRINTWIDGET_0_idle_cycles_mask,
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PRINTWIDGET_0_print_offsets,
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PRINTWIDGET_0_format_strings,
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PRINTWIDGET_0_argument_counts,
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PRINTWIDGET_0_argument_widths,
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PRINTWIDGET_0_DMA_ADDR);
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add_endpoint(print_endpoint);
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#endif
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#endif
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// Add functions you'd like to periodically invoke on a paused simulator here.
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@ -348,7 +368,7 @@ uint64_t host_mem_offset = -0x80000000LL;
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bool firesim_top_t::simulation_complete() {
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bool is_complete = false;
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for (auto e: endpoints) {
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for (auto &e: endpoints) {
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is_complete |= e->terminate();
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}
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return is_complete;
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@ -362,7 +382,7 @@ uint64_t firesim_top_t::profile_models(){
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}
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int firesim_top_t::exit_code(){
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for (auto e: endpoints) {
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for (auto &e: endpoints) {
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if (e->exit_code())
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return e->exit_code();
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}
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@ -371,11 +391,11 @@ int firesim_top_t::exit_code(){
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void firesim_top_t::run() {
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for (auto e: fpga_models) {
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for (auto &e: fpga_models) {
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e->init();
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}
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for (auto e: endpoints) {
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for (auto &e: endpoints) {
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e->init();
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}
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@ -394,7 +414,7 @@ void firesim_top_t::run() {
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run_scheduled_tasks();
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step(get_largest_stepsize(), false);
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while(!done() && !simulation_complete()){
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for (auto e: endpoints) e->tick();
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for (auto &e: endpoints) e->tick();
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}
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}
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@ -425,5 +445,8 @@ void firesim_top_t::run() {
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for (auto e: fpga_models) {
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e->finish();
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}
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#ifdef PRINTWIDGET_0_PRESENT
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print_endpoint->finish();
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#endif
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}
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@ -1,11 +1,15 @@
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#ifndef __FIRESIM_TOP_H
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#define __FIRESIM_TOP_H
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#include <memory>
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#include "simif.h"
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#include "endpoints/endpoint.h"
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#include "endpoints/fpga_model.h"
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#include "systematic_scheduler.h"
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#include "endpoints/synthesized_prints.h"
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class firesim_top_t: virtual simif_t, public systematic_scheduler_t
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{
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public:
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@ -16,15 +20,19 @@ class firesim_top_t: virtual simif_t, public systematic_scheduler_t
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protected:
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void add_endpoint(endpoint_t* endpoint) {
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endpoints.push_back(endpoint);
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endpoints.push_back(std::unique_ptr<endpoint_t>(endpoint));
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}
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private:
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// Memory mapped endpoints bound to software models
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std::vector<endpoint_t*> endpoints;
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std::vector<std::unique_ptr<endpoint_t> > endpoints;
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// FPGA-hosted models with programmable registers & instrumentation
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std::vector<FpgaModel*> fpga_models;
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#ifdef PRINTWIDGET_struct_guard
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synthesized_prints_t * print_endpoint;
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#endif
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// profile interval: # of cycles to advance before profiling instrumentation registers in models
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uint64_t profile_interval = -1;
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uint64_t profile_models();
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@ -27,6 +27,10 @@
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#include "Stack.h"
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#elif defined DESIGNNAME_AssertModule
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#include "AssertModule.h"
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#elif defined DESIGNNAME_PrintfModule
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#include "PrintfModule.h"
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#elif defined DESIGNNAME_NarrowPrintfModule
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#include "NarrowPrintfModule.h"
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#endif
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class dut_emul_t:
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@ -0,0 +1,22 @@
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//See LICENSE for license details.
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#include "PrintfModule.h"
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class NarrowPrintfModule_t: public print_module_t, virtual simif_t
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{
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public:
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NarrowPrintfModule_t(int argc, char** argv): print_module_t(argc, argv) {};
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virtual void run() {
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print_endpoint->init();
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poke(reset, 1);
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poke(enable, 0);
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step(1);
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poke(enable, 1);
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poke(reset, 0);
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step(4);
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// Test idle-cycle rollover
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poke(enable, 0);
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step(256);
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poke(enable, 1);
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run_and_collect_prints(256);
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};
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};
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@ -0,0 +1,54 @@
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//See LICENSE for license details.
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#include <memory>
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#include "simif.h"
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#include "endpoints/synthesized_prints.h"
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class print_module_t: virtual simif_t
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{
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public:
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std::unique_ptr<synthesized_prints_t> print_endpoint;
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print_module_t(int argc, char** argv) {
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PRINTWIDGET_0_substruct_create;
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std::vector<std::string> args(argv + 1, argv + argc);
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print_endpoint = std::unique_ptr<synthesized_prints_t>(new synthesized_prints_t(this,
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args,
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PRINTWIDGET_0_substruct,
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PRINTWIDGET_0_print_count,
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PRINTWIDGET_0_token_bytes,
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PRINTWIDGET_0_idle_cycles_mask,
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PRINTWIDGET_0_print_offsets,
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PRINTWIDGET_0_format_strings,
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PRINTWIDGET_0_argument_counts,
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PRINTWIDGET_0_argument_widths,
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PRINTWIDGET_0_DMA_ADDR));
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};
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void run_and_collect_prints(int cycles) {
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step(cycles, false);
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while (!done()) {
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print_endpoint->tick();
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}
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print_endpoint->finish();
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};
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};
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#ifdef DESIGNNAME_PrintfModule
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class PrintfModule_t: public print_module_t, virtual simif_t
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{
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public:
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PrintfModule_t(int argc, char** argv): print_module_t(argc, argv) {};
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virtual void run() {
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print_endpoint->init();
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poke(reset, 1);
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poke(a, 0);
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poke(b, 0);
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step(1);
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poke(reset, 0);
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step(1);
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poke(a, 1);
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poke(b, 1);
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run_and_collect_prints(256);
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};
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};
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#endif //DESIGNNAME_PrintfModule
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@ -34,7 +34,7 @@ driver_dir = $(firesim_base_dir)/src/main/cc
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DRIVER_H = $(shell find $(driver_dir) -name "*.h")
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DRIVER_CC := $(driver_dir)/midasexamples/Driver.cc
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TARGET_CXX_FLAGS := -DDESIGNDRIVERCLASS=$(DESIGN)_t -DDESIGNNAME_$(DESIGN) -I$(driver_dir) -I$(driver_dir)/midasexamples
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TARGET_CXX_FLAGS := -DDESIGNDRIVERCLASS=$(DESIGN)_t -DDESIGNNAME_$(DESIGN) -I$(driver_dir) -I$(driver_dir)/midasexamples -g
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TARGET_LD_FLAGS :=
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##########################
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@ -31,6 +31,12 @@ class WithSynthAsserts extends Config((site, here, up) => {
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case EndpointKey => EndpointMap(Seq(new midas.widgets.AssertBundleEndpoint)) ++ up(EndpointKey)
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})
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||||
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||||
// Experimental: mixing this in will enable print synthesis
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||||
class WithPrintfSynthesis extends Config((site, here, up) => {
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case midas.SynthPrints => true
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case EndpointKey => EndpointMap(Seq(new midas.widgets.PrintRecordEndpoint)) ++ up(EndpointKey)
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})
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class WithSerialWidget extends Config((site, here, up) => {
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case EndpointKey => up(EndpointKey) ++ EndpointMap(Seq(new SimSerialIO))
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})
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|
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@ -10,6 +10,7 @@ import junctions._
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// This is incomplete and must be mixed into a complete platform config
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class DefaultMIDASConfig extends Config(new Config((site, here, up) => {
|
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case SynthAsserts => true
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case SynthPrints => true
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}) ++ new Config(new firesim.firesim.WithDefaultMemModel))
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||||
|
||||
class PointerChaserConfig extends Config((site, here, up) => {
|
||||
|
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@ -18,7 +18,7 @@ trait GeneratorUtils {
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Class.forName(s"firesim.midasexamples.${targetName}")
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.getConstructors.head
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.newInstance()
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||||
.asInstanceOf[chisel3.Module]
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.asInstanceOf[chisel3.experimental.RawModule]
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||||
}
|
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def midasParams = (platform match {
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case midas.F1 => new Config(new DefaultMIDASConfig ++ new midas.F1Config)
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||||
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@ -0,0 +1,53 @@
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//See LICENSE for license details.
|
||||
|
||||
package firesim.midasexamples
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||||
|
||||
import chisel3._
|
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import chisel3.util.LFSR16
|
||||
import chisel3.experimental.MultiIOModule
|
||||
|
||||
import midas.targetutils.SynthesizePrintf
|
||||
|
||||
class PrintfModule extends MultiIOModule {
|
||||
val a = IO(Input(Bool()))
|
||||
val b = IO(Input(Bool()))
|
||||
|
||||
val cycle = RegInit(0.U(16.W))
|
||||
|
||||
when(a) { cycle := cycle + 1.U }
|
||||
|
||||
// Printf format strings must be prefixed with "SYNTHESIZED_PRINT CYCLE: %d"
|
||||
// so they can be pulled out of RTL simulators log and sorted within a cycle
|
||||
// As the printf order will be different betwen RTL simulator and synthesized stream
|
||||
printf(SynthesizePrintf("SYNTHESIZED_PRINT CYCLE: %d\n", cycle))
|
||||
|
||||
val wideArgument = VecInit(Seq.fill(33)(WireInit(cycle))).asUInt
|
||||
printf(SynthesizePrintf("SYNTHESIZED_PRINT CYCLE: %d wideArgument: %x\n", cycle, wideArgument)) // argument width > DMA width
|
||||
|
||||
val childInst = Module(new PrintfModuleChild)
|
||||
childInst.c := a
|
||||
childInst.cycle := cycle
|
||||
|
||||
printf(SynthesizePrintf("thi$!sn+taS/\neName", "SYNTHESIZED_PRINT CYCLE: %d constantArgument: %x\n", cycle, 1.U(8.W)))
|
||||
}
|
||||
|
||||
class PrintfModuleChild extends MultiIOModule {
|
||||
val c = IO(Input(Bool()))
|
||||
val cycle = IO(Input(UInt(16.W)))
|
||||
|
||||
val lfsr = chisel3.util.LFSR16(c)
|
||||
printf(SynthesizePrintf("SYNTHESIZED_PRINT CYCLE: %d LFSR: %x\n", cycle, lfsr))
|
||||
|
||||
//when (lsfr(0)) {
|
||||
// printf(SynthesizePrintf(p"SYNTHESIZED_PRINT CYCLE: ${cycle} LFSR is odd"))
|
||||
//}
|
||||
}
|
||||
|
||||
class NarrowPrintfModule extends MultiIOModule {
|
||||
val enable = IO(Input(Bool()))
|
||||
val cycle = RegInit(0.U(12.W))
|
||||
cycle := cycle + 1.U
|
||||
when(LFSR16()(0) & LFSR16()(0) & enable) {
|
||||
printf(SynthesizePrintf("SYNTHESIZED_PRINT CYCLE: %d\n", cycle(5,0)))
|
||||
}
|
||||
}
|
||||
|
|
@ -3,6 +3,7 @@ package firesim.midasexamples
|
|||
|
||||
import java.io.File
|
||||
import scala.sys.process.{stringSeqToProcess, ProcessLogger}
|
||||
import scala.io.Source
|
||||
|
||||
abstract class TutorialSuite(
|
||||
val targetName: String, // See GeneratorUtils
|
||||
|
|
@ -69,6 +70,26 @@ abstract class TutorialSuite(
|
|||
ignore should s"pass in ${testEnv}" in { }
|
||||
}
|
||||
}
|
||||
|
||||
// Checks that the synthesized print log in ${genDir}/${synthPrintLog} matches the
|
||||
// printfs from the RTL simulator
|
||||
def diffSynthesizedPrints(synthPrintLog: String) {
|
||||
behavior of "synthesized print log"
|
||||
it should "match the logs produced by the verilated design" in {
|
||||
def printLines(filename: File): Seq[String] = {
|
||||
val lines = Source.fromFile(filename).getLines.toList
|
||||
lines.filter(_.startsWith("SYNTHESIZED_PRINT")).sorted
|
||||
}
|
||||
|
||||
val verilatedOutput = printLines(new File(outDir, s"/${targetName}.verilator.out"))
|
||||
val synthPrintOutput = printLines(new File(genDir, s"/${synthPrintLog}"))
|
||||
assert(verilatedOutput.size == synthPrintOutput.size && verilatedOutput.nonEmpty)
|
||||
for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) {
|
||||
assert(vPrint == sPrint)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
clean
|
||||
mkdirs
|
||||
compile
|
||||
|
|
@ -90,3 +111,11 @@ class StackF1Test extends TutorialSuite("Stack", midas.F1, 8)
|
|||
class RiscF1Test extends TutorialSuite("Risc", midas.F1, 64)
|
||||
class RiscSRAMF1Test extends TutorialSuite("RiscSRAM", midas.F1, 64)
|
||||
class AssertModuleF1Test extends TutorialSuite("AssertModule", midas.F1)
|
||||
class PrintfModuleF1Test extends TutorialSuite("PrintfModule", midas.F1,
|
||||
simulationArgs = Seq("+print-human-readable", "+printfile=synthprinttest.out")) {
|
||||
diffSynthesizedPrints("synthprinttest.out")
|
||||
}
|
||||
class NarrowPrintfModuleF1Test extends TutorialSuite("NarrowPrintfModule", midas.F1,
|
||||
simulationArgs = Seq("+print-human-readable", "+printfile=synthprinttest.out")) {
|
||||
diffSynthesizedPrints("synthprinttest.out")
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue