From c85fda64d87c7ed342bee22f907357ce9e45bb6a Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 1 Dec 2018 22:45:04 -0800 Subject: [PATCH 01/26] [midasexamples] Cast to RawModule, not LegacyModule in generator --- sim/src/main/scala/midasexamples/Generator.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/src/main/scala/midasexamples/Generator.scala b/sim/src/main/scala/midasexamples/Generator.scala index 2fb8d772..b8629961 100644 --- a/sim/src/main/scala/midasexamples/Generator.scala +++ b/sim/src/main/scala/midasexamples/Generator.scala @@ -18,7 +18,7 @@ trait GeneratorUtils { Class.forName(s"firesim.midasexamples.${targetName}") .getConstructors.head .newInstance() - .asInstanceOf[chisel3.Module] + .asInstanceOf[chisel3.experimental.RawModule] } def midasParams = (platform match { case midas.F1 => new Config(new DefaultMIDASConfig ++ new midas.F1Config) From 981fddbde040202996bcc13aaf5b0732eefa9723 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 1 Dec 2018 22:48:17 -0800 Subject: [PATCH 02/26] [WIP] Add a failing PrintModule midas example --- sim/firrtl | 2 +- sim/midas | 2 +- sim/src/main/cc/midasexamples/Driver.cc | 2 ++ sim/src/main/cc/midasexamples/PrintfModule.h | 12 +++++++++++ .../scala/midasexamples/PrintfModule.scala | 21 +++++++++++++++++++ .../scala/midasexamples/TutorialSuite.scala | 1 + 6 files changed, 38 insertions(+), 2 deletions(-) create mode 100644 sim/src/main/cc/midasexamples/PrintfModule.h create mode 100644 sim/src/main/scala/midasexamples/PrintfModule.scala diff --git a/sim/firrtl b/sim/firrtl index ba12915e..0a4bcaa4 160000 --- a/sim/firrtl +++ b/sim/firrtl @@ -1 +1 @@ -Subproject commit ba12915e9b93685107c503b3f91b96d491c48459 +Subproject commit 0a4bcaa4053aca16f21f899ba76b1b751cfb47b3 diff --git a/sim/midas b/sim/midas index d9251aea..b4260714 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit d9251aea8bc7c4f65ea46013e319d41cbdeb1944 +Subproject commit b4260714ec7182c297a3c1d02e7df833a1d3eb1f diff --git a/sim/src/main/cc/midasexamples/Driver.cc b/sim/src/main/cc/midasexamples/Driver.cc index d6b660e3..fb820f66 100644 --- a/sim/src/main/cc/midasexamples/Driver.cc +++ b/sim/src/main/cc/midasexamples/Driver.cc @@ -27,6 +27,8 @@ #include "Stack.h" #elif defined DESIGNNAME_AssertModule #include "AssertModule.h" +#elif defined DESIGNNAME_PrintfModule +#include "PrintfModule.h" #endif class dut_emul_t: diff --git a/sim/src/main/cc/midasexamples/PrintfModule.h b/sim/src/main/cc/midasexamples/PrintfModule.h new file mode 100644 index 00000000..e0590d17 --- /dev/null +++ b/sim/src/main/cc/midasexamples/PrintfModule.h @@ -0,0 +1,12 @@ +//See LICENSE for license details. + +#include "simif.h" + +class PrintfModule_t: virtual simif_t +{ +public: + PrintModule_t(int argc, char** argv) { }; + void run() { + expect(false, "Flesh me out"); + }; +}; diff --git a/sim/src/main/scala/midasexamples/PrintfModule.scala b/sim/src/main/scala/midasexamples/PrintfModule.scala new file mode 100644 index 00000000..dcd4db6d --- /dev/null +++ b/sim/src/main/scala/midasexamples/PrintfModule.scala @@ -0,0 +1,21 @@ +//See LICENSE for license details. + +package firesim.midasexamples + +import chisel3._ +import chisel3.experimental.MultiIOModule + +import midas.targetutils.SynthesizablePrintfs + +class PrintfModule extends MultiIOModule with SynthesizablePrintfs { + val a = IO(Input(Bool())) + val b = IO(Input(Bool())) + + val cycle = RegInit(0.U(16.W)) + + when(a) { cycle := cycle + 1.U } + + printf(synthesizePrintf("A: %d\n", cycle)) + when(b) { printf(synthesizePrintf("B asserted\n")) } // Argument-less print +} + diff --git a/sim/src/test/scala/midasexamples/TutorialSuite.scala b/sim/src/test/scala/midasexamples/TutorialSuite.scala index 81f77d45..18127d64 100644 --- a/sim/src/test/scala/midasexamples/TutorialSuite.scala +++ b/sim/src/test/scala/midasexamples/TutorialSuite.scala @@ -90,3 +90,4 @@ class StackF1Test extends TutorialSuite("Stack", midas.F1, 8) class RiscF1Test extends TutorialSuite("Risc", midas.F1, 64) class RiscSRAMF1Test extends TutorialSuite("RiscSRAM", midas.F1, 64) class AssertModuleF1Test extends TutorialSuite("AssertModule", midas.F1) +class PrintfModuleF1Test extends TutorialSuite("PrintfModule", midas.F1) From b495870f564630e56156ad6f04dfcd978d9fb029 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 4 Dec 2018 08:52:43 -0800 Subject: [PATCH 03/26] [WIP] Update printf annotator usage --- sim/src/main/cc/midasexamples/PrintfModule.h | 2 +- sim/src/main/scala/midasexamples/PrintfModule.scala | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/sim/src/main/cc/midasexamples/PrintfModule.h b/sim/src/main/cc/midasexamples/PrintfModule.h index e0590d17..bc0efd8b 100644 --- a/sim/src/main/cc/midasexamples/PrintfModule.h +++ b/sim/src/main/cc/midasexamples/PrintfModule.h @@ -5,7 +5,7 @@ class PrintfModule_t: virtual simif_t { public: - PrintModule_t(int argc, char** argv) { }; + PrintfModule_t(int argc, char** argv) { }; void run() { expect(false, "Flesh me out"); }; diff --git a/sim/src/main/scala/midasexamples/PrintfModule.scala b/sim/src/main/scala/midasexamples/PrintfModule.scala index dcd4db6d..9bec3a99 100644 --- a/sim/src/main/scala/midasexamples/PrintfModule.scala +++ b/sim/src/main/scala/midasexamples/PrintfModule.scala @@ -5,9 +5,9 @@ package firesim.midasexamples import chisel3._ import chisel3.experimental.MultiIOModule -import midas.targetutils.SynthesizablePrintfs +import midas.targetutils.SynthesizePrintf -class PrintfModule extends MultiIOModule with SynthesizablePrintfs { +class PrintfModule extends MultiIOModule { val a = IO(Input(Bool())) val b = IO(Input(Bool())) @@ -15,7 +15,7 @@ class PrintfModule extends MultiIOModule with SynthesizablePrintfs { when(a) { cycle := cycle + 1.U } - printf(synthesizePrintf("A: %d\n", cycle)) - when(b) { printf(synthesizePrintf("B asserted\n")) } // Argument-less print + printf(SynthesizePrintf("A: %d\n", cycle)) + when(b) { printf(SynthesizePrintf("B asserted\n")) } // Argument-less print } From c15d43925939ab20c70512dbe01370033b415044 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 9 Dec 2018 21:24:56 -0800 Subject: [PATCH 04/26] Expand PrintfModule to have a child module --- sim/firrtl | 2 +- sim/src/main/scala/firesim/SimConfigs.scala | 5 +++++ .../scala/midasexamples/.Generator.scala.swp | Bin 0 -> 12288 bytes .../main/scala/midasexamples/PrintfModule.scala | 12 ++++++++++++ 4 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 sim/src/main/scala/midasexamples/.Generator.scala.swp diff --git a/sim/firrtl b/sim/firrtl index 0a4bcaa4..380c233b 160000 --- a/sim/firrtl +++ b/sim/firrtl @@ -1 +1 @@ -Subproject commit 0a4bcaa4053aca16f21f899ba76b1b751cfb47b3 +Subproject commit 380c233b43c2de53b0ee15a39e9364d438066b9f diff --git a/sim/src/main/scala/firesim/SimConfigs.scala b/sim/src/main/scala/firesim/SimConfigs.scala index 864feafa..dd22ad57 100644 --- a/sim/src/main/scala/firesim/SimConfigs.scala +++ b/sim/src/main/scala/firesim/SimConfigs.scala @@ -31,6 +31,11 @@ class WithSynthAsserts extends Config((site, here, up) => { case EndpointKey => EndpointMap(Seq(new midas.widgets.AssertBundleEndpoint)) ++ up(EndpointKey) }) +// Experimental: mixing this in will enable print synthesis +class WithPrintSynthesis extends Config((site, here, up) => { + case EndpointKey => EndpointMap(Seq(new midas.widgets.PrintRecordEndpoint)) ++ up(EndpointKey) +}) + class WithSerialWidget extends Config((site, here, up) => { case EndpointKey => up(EndpointKey) ++ EndpointMap(Seq(new SimSerialIO)) }) diff --git a/sim/src/main/scala/midasexamples/.Generator.scala.swp b/sim/src/main/scala/midasexamples/.Generator.scala.swp new file mode 100644 index 0000000000000000000000000000000000000000..d8613d51a46918a46cbeb50fdcfa1875c3d96bb6 GIT binary patch literal 12288 zcmeI2L2n#26vy41Qc3`U#MvxGnx%=S+i<8N0z{hxt<;o|O(_zsDreTS>vqO7wY|-T z)hd@>IG`d9d;_kCF93W1gt&15#0>;o_z3(xGdsIWP%j)1$RqtTGq&gXy`SH+w2F@| zzth>HSJ`EP>ls3Rd$@9I`NGRfzu0(zKKJa6GsAp?C*TQq0-k^;;0bsFo`5Id3H*Nv*!&zhMR-e9 zh^^{=?l1T1)!#e;PrwuK1Uvyxz!UHUJONL@6YvB)0Z-sRNPzbUd32tT>a z|NrtLeE2g!1wQ`g z@|P#z33vjYfG6Mycmkflze-?2D2=i-mx;iWd&4`9bte2vtf;&?QndBSa+>6A)CRc5If=6R;A=uxTYE)J7+W!h-Y%r@dy!&xp4kFwns zdJ_Kr34OqmnXOIAb>9T*O`5vnsdPL)sxQ>G)O53OYZrb8#o#MVH%o2HqEXoEJQWyO z3}`h;c63)nmexmAsTf(IdWLT0IX#wkFzdQuWnwTfaY#xm#_H@yXr={%K4I;WnhttH zyGl#1oC`e>Pl?`y$%A5a&@6%|4bd|CeXeCne53cl`G6oLHrU%-BQCm2oR$0AR798Ju;~&0^g&R;qsG?OY_Th5nNni-^jI zo8Sot$|ziJRcDS_&W#a+gshTnO?e744QsgwoX@hE+)(#)TJ;> z+Ua^16Ebe5PQ4Ys7Y(El$vP9GTxe95vOHl2{CF?x4HI#j6rYrT7@V7a8I;(nUWOcp zPsq$+grnDn4FrBamYwYcI2kg)6#>e1O1bcQdTg6r9M39cGGC~70I0I$*z9LG4=!|j zfW1Kn&7c6b&{(mVLtnaD>?Vzcp>79&ZI@pt9$G>ScXue(h9)u+3fpZ@SdJZs Gkv{>>`zDb9 literal 0 HcmV?d00001 diff --git a/sim/src/main/scala/midasexamples/PrintfModule.scala b/sim/src/main/scala/midasexamples/PrintfModule.scala index 9bec3a99..d24162cf 100644 --- a/sim/src/main/scala/midasexamples/PrintfModule.scala +++ b/sim/src/main/scala/midasexamples/PrintfModule.scala @@ -17,5 +17,17 @@ class PrintfModule extends MultiIOModule { printf(SynthesizePrintf("A: %d\n", cycle)) when(b) { printf(SynthesizePrintf("B asserted\n")) } // Argument-less print + val childInst = Module(new PrintfModuleChild) + childInst.c := a + childInst.d := cycle +} + +class PrintfModuleChild extends MultiIOModule { + val c = IO(Input(Bool())) + val d = IO(Input(UInt(16.W))) + + when (c ^ d(0) && d > 16.U) { + printf(SynthesizePrintf("C: %b, D: %d\n", c, d)) + } } From 3dfdaf20a4234a34e04b2df0c36551cd814411a2 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 9 Dec 2018 21:25:28 -0800 Subject: [PATCH 05/26] Fix a bug in firrtl.jar timestamping --- sim/Makefile | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/sim/Makefile b/sim/Makefile index 6b02f1d2..31acc66c 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -23,12 +23,13 @@ SBT_FLAGS ?= -J-Xmx16G -J-Xss8M -J-XX:MaxPermSize=256M -J-XX:MaxMetaspaceSize=51 firesim_base_dir := $(abspath .) # Manage the FIRRTL dependency manually -FIRRTL_JAR ?= $(firesim_base_dir)/lib/firrtl.jar FIRRTL_SUBMODULE_DIR ?= $(firesim_base_dir)/firrtl +FIRRTL_JAR ?= $(FIRRTL_SUBMODULE_DIR)/utils/bin/firrtl.jar $(FIRRTL_JAR): $(shell find $(FIRRTL_SUBMODULE_DIR)/src/main/scala -iname "*.scala") $(MAKE) -C $(FIRRTL_SUBMODULE_DIR) SBT="$(SBT) $(SBT_FLAGS)" root_dir=$(FIRRTL_SUBMODULE_DIR) build-scala - mkdir -p $(@D) - cp -p $(FIRRTL_SUBMODULE_DIR)/utils/bin/firrtl.jar $(FIRRTL_JAR) + touch $(FIRRTL_JAR) + mkdir -p $(firesim_base_dir)/lib + cp -p $(FIRRTL_JAR) $(firesim_base_dir)/lib/ firrtl: $(FIRRTL_JAR) .PHONY: firrtl From 745e3ab5814e1989340e619b29153c0e58efd968 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 10 Dec 2018 01:16:40 -0800 Subject: [PATCH 06/26] [midasexamples] Add -g to target flags --- sim/src/main/makefrag/midasexamples/Makefrag | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/src/main/makefrag/midasexamples/Makefrag b/sim/src/main/makefrag/midasexamples/Makefrag index 4ef5971d..00d2be6c 100644 --- a/sim/src/main/makefrag/midasexamples/Makefrag +++ b/sim/src/main/makefrag/midasexamples/Makefrag @@ -34,7 +34,7 @@ driver_dir = $(firesim_base_dir)/src/main/cc DRIVER_H = $(shell find $(driver_dir) -name "*.h") DRIVER_CC := $(driver_dir)/midasexamples/Driver.cc -TARGET_CXX_FLAGS := -DDESIGNDRIVERCLASS=$(DESIGN)_t -DDESIGNNAME_$(DESIGN) -I$(driver_dir) -I$(driver_dir)/midasexamples +TARGET_CXX_FLAGS := -DDESIGNDRIVERCLASS=$(DESIGN)_t -DDESIGNNAME_$(DESIGN) -I$(driver_dir) -I$(driver_dir)/midasexamples -g TARGET_LD_FLAGS := ########################## From 0dc7f528eeb1b881c882352b1b6e4ba579ac84ee Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 10 Dec 2018 01:19:45 -0800 Subject: [PATCH 07/26] [midasexamples] Properly instantiate print endpoint --- sim/midas | 2 +- sim/src/main/cc/midasexamples/PrintfModule.h | 26 +++++++++++++++++- .../scala/midasexamples/.Generator.scala.swp | Bin 12288 -> 0 bytes 3 files changed, 26 insertions(+), 2 deletions(-) delete mode 100644 sim/src/main/scala/midasexamples/.Generator.scala.swp diff --git a/sim/midas b/sim/midas index b4260714..f4c666d0 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit b4260714ec7182c297a3c1d02e7df833a1d3eb1f +Subproject commit f4c666d00f97803c2cd7caaa30452da91b8e8b00 diff --git a/sim/src/main/cc/midasexamples/PrintfModule.h b/sim/src/main/cc/midasexamples/PrintfModule.h index bc0efd8b..fd617611 100644 --- a/sim/src/main/cc/midasexamples/PrintfModule.h +++ b/sim/src/main/cc/midasexamples/PrintfModule.h @@ -1,12 +1,36 @@ //See LICENSE for license details. #include "simif.h" +#include "endpoints/synthesized_prints.h" class PrintfModule_t: virtual simif_t { public: - PrintfModule_t(int argc, char** argv) { }; + synthesized_prints_t * print_endpoint; + PrintfModule_t(int argc, char** argv) { + PRINTWIDGET_0_substruct_create; + print_endpoint = new synthesized_prints_t(this, + PRINTWIDGET_0_substruct, + PRINTWIDGET_0_print_count, + PRINTWIDGET_0_print_offsets, + PRINTWIDGET_0_format_strings, + PRINTWIDGET_0_argument_counts, + PRINTWIDGET_0_argument_widths, + PRINTWIDGET_0_DMA_ADDR); + }; void run() { + poke(reset, 1); + poke(a, 0); + poke(b, 0); + step(1); + poke(reset, 0); + step(1); + poke(a, 1); + poke(b, 1); + step(128, false); + while (!done()) { + print_endpoint->tick(); + } expect(false, "Flesh me out"); }; }; diff --git a/sim/src/main/scala/midasexamples/.Generator.scala.swp b/sim/src/main/scala/midasexamples/.Generator.scala.swp deleted file mode 100644 index d8613d51a46918a46cbeb50fdcfa1875c3d96bb6..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 12288 zcmeI2L2n#26vy41Qc3`U#MvxGnx%=S+i<8N0z{hxt<;o|O(_zsDreTS>vqO7wY|-T z)hd@>IG`d9d;_kCF93W1gt&15#0>;o_z3(xGdsIWP%j)1$RqtTGq&gXy`SH+w2F@| zzth>HSJ`EP>ls3Rd$@9I`NGRfzu0(zKKJa6GsAp?C*TQq0-k^;;0bsFo`5Id3H*Nv*!&zhMR-e9 zh^^{=?l1T1)!#e;PrwuK1Uvyxz!UHUJONL@6YvB)0Z-sRNPzbUd32tT>a z|NrtLeE2g!1wQ`g z@|P#z33vjYfG6Mycmkflze-?2D2=i-mx;iWd&4`9bte2vtf;&?QndBSa+>6A)CRc5If=6R;A=uxTYE)J7+W!h-Y%r@dy!&xp4kFwns zdJ_Kr34OqmnXOIAb>9T*O`5vnsdPL)sxQ>G)O53OYZrb8#o#MVH%o2HqEXoEJQWyO z3}`h;c63)nmexmAsTf(IdWLT0IX#wkFzdQuWnwTfaY#xm#_H@yXr={%K4I;WnhttH zyGl#1oC`e>Pl?`y$%A5a&@6%|4bd|CeXeCne53cl`G6oLHrU%-BQCm2oR$0AR798Ju;~&0^g&R;qsG?OY_Th5nNni-^jI zo8Sot$|ziJRcDS_&W#a+gshTnO?e744QsgwoX@hE+)(#)TJ;> z+Ua^16Ebe5PQ4Ys7Y(El$vP9GTxe95vOHl2{CF?x4HI#j6rYrT7@V7a8I;(nUWOcp zPsq$+grnDn4FrBamYwYcI2kg)6#>e1O1bcQdTg6r9M39cGGC~70I0I$*z9LG4=!|j zfW1Kn&7c6b&{(mVLtnaD>?Vzcp>79&ZI@pt9$G>ScXue(h9)u+3fpZ@SdJZs Gkv{>>`zDb9 From 249ab270823073e10f9d14af70f644fdf7799c73 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 11 Dec 2018 10:27:06 -0800 Subject: [PATCH 08/26] [midasexamples] Add print plusargs --- sim/midas | 2 +- sim/src/main/cc/midasexamples/PrintfModule.h | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/sim/midas b/sim/midas index f4c666d0..cecdcf3c 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit f4c666d00f97803c2cd7caaa30452da91b8e8b00 +Subproject commit cecdcf3c388ffc2fbc63f0bd7b2c7a8b18ac3d8f diff --git a/sim/src/main/cc/midasexamples/PrintfModule.h b/sim/src/main/cc/midasexamples/PrintfModule.h index fd617611..0252c6fd 100644 --- a/sim/src/main/cc/midasexamples/PrintfModule.h +++ b/sim/src/main/cc/midasexamples/PrintfModule.h @@ -9,7 +9,9 @@ public: synthesized_prints_t * print_endpoint; PrintfModule_t(int argc, char** argv) { PRINTWIDGET_0_substruct_create; + std::vector args(argv + 1, argv + argc); print_endpoint = new synthesized_prints_t(this, + args, PRINTWIDGET_0_substruct, PRINTWIDGET_0_print_count, PRINTWIDGET_0_print_offsets, @@ -33,4 +35,8 @@ public: } expect(false, "Flesh me out"); }; + + ~PrintfModule_t() { + delete print_endpoint; + }; }; From 886c987210785172d84c38717e39f7884d617a0f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 11 Dec 2018 13:09:06 -0800 Subject: [PATCH 09/26] [midasexamples] Update initialization and teardown of print widget --- sim/midas | 2 +- sim/src/main/cc/midasexamples/PrintfModule.h | 32 ++++++++++---------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/sim/midas b/sim/midas index cecdcf3c..f417cb21 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit cecdcf3c388ffc2fbc63f0bd7b2c7a8b18ac3d8f +Subproject commit f417cb21f6b4115610c0c1075336d4798a79cbb7 diff --git a/sim/src/main/cc/midasexamples/PrintfModule.h b/sim/src/main/cc/midasexamples/PrintfModule.h index 0252c6fd..71fb46b8 100644 --- a/sim/src/main/cc/midasexamples/PrintfModule.h +++ b/sim/src/main/cc/midasexamples/PrintfModule.h @@ -1,26 +1,30 @@ //See LICENSE for license details. +#include + #include "simif.h" #include "endpoints/synthesized_prints.h" class PrintfModule_t: virtual simif_t { public: - synthesized_prints_t * print_endpoint; + std::unique_ptr print_endpoint; PrintfModule_t(int argc, char** argv) { PRINTWIDGET_0_substruct_create; std::vector args(argv + 1, argv + argc); - print_endpoint = new synthesized_prints_t(this, - args, - PRINTWIDGET_0_substruct, - PRINTWIDGET_0_print_count, - PRINTWIDGET_0_print_offsets, - PRINTWIDGET_0_format_strings, - PRINTWIDGET_0_argument_counts, - PRINTWIDGET_0_argument_widths, - PRINTWIDGET_0_DMA_ADDR); + print_endpoint = std::unique_ptr(new synthesized_prints_t(this, + args, + PRINTWIDGET_0_substruct, + PRINTWIDGET_0_print_count, + PRINTWIDGET_0_print_offsets, + PRINTWIDGET_0_format_strings, + PRINTWIDGET_0_argument_counts, + PRINTWIDGET_0_argument_widths, + PRINTWIDGET_0_DMA_ADDR)); }; - void run() { + + virtual void run() { + print_endpoint->init(); poke(reset, 1); poke(a, 0); poke(b, 0); @@ -33,10 +37,6 @@ public: while (!done()) { print_endpoint->tick(); } - expect(false, "Flesh me out"); - }; - - ~PrintfModule_t() { - delete print_endpoint; + print_endpoint->finish(); }; }; From b64b87f5fb1e23e2044f564d5af574242e404046 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 11 Dec 2018 20:11:04 -0800 Subject: [PATCH 10/26] [Print] Support synthesized printfs that exceed DMA width --- sim/midas | 2 +- sim/src/main/cc/midasexamples/PrintfModule.h | 17 +++++++++-------- .../main/scala/midasexamples/PrintfModule.scala | 4 ++++ 3 files changed, 14 insertions(+), 9 deletions(-) diff --git a/sim/midas b/sim/midas index f417cb21..3a1601fc 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit f417cb21f6b4115610c0c1075336d4798a79cbb7 +Subproject commit 3a1601fcb254936f6bdfc22e246d2d0fa65eeae7 diff --git a/sim/src/main/cc/midasexamples/PrintfModule.h b/sim/src/main/cc/midasexamples/PrintfModule.h index 71fb46b8..3ef9f004 100644 --- a/sim/src/main/cc/midasexamples/PrintfModule.h +++ b/sim/src/main/cc/midasexamples/PrintfModule.h @@ -13,14 +13,15 @@ public: PRINTWIDGET_0_substruct_create; std::vector args(argv + 1, argv + argc); print_endpoint = std::unique_ptr(new synthesized_prints_t(this, - args, - PRINTWIDGET_0_substruct, - PRINTWIDGET_0_print_count, - PRINTWIDGET_0_print_offsets, - PRINTWIDGET_0_format_strings, - PRINTWIDGET_0_argument_counts, - PRINTWIDGET_0_argument_widths, - PRINTWIDGET_0_DMA_ADDR)); + args, + PRINTWIDGET_0_substruct, + PRINTWIDGET_0_print_count, + PRINTWIDGET_0_token_bytes, + PRINTWIDGET_0_print_offsets, + PRINTWIDGET_0_format_strings, + PRINTWIDGET_0_argument_counts, + PRINTWIDGET_0_argument_widths, + PRINTWIDGET_0_DMA_ADDR)); }; virtual void run() { diff --git a/sim/src/main/scala/midasexamples/PrintfModule.scala b/sim/src/main/scala/midasexamples/PrintfModule.scala index d24162cf..5bb0004c 100644 --- a/sim/src/main/scala/midasexamples/PrintfModule.scala +++ b/sim/src/main/scala/midasexamples/PrintfModule.scala @@ -17,6 +17,10 @@ class PrintfModule extends MultiIOModule { printf(SynthesizePrintf("A: %d\n", cycle)) when(b) { printf(SynthesizePrintf("B asserted\n")) } // Argument-less print + + val wideArgument = VecInit(Seq.fill(33)(WireInit(cycle))).asUInt + printf(SynthesizePrintf("wideArgument: %x\n", wideArgument)) // argument width > DMA width + val childInst = Module(new PrintfModuleChild) childInst.c := a childInst.d := cycle From 70f093fd8cc26ccda0f35f98d44e480640de1c10 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 12 Dec 2018 02:08:33 -0800 Subject: [PATCH 11/26] [Driver] Properly invoke endpoint dtors --- sim/midas | 2 +- sim/src/main/cc/firesim/firesim_top.cc | 10 +++++----- sim/src/main/cc/firesim/firesim_top.h | 6 ++++-- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/sim/midas b/sim/midas index 3a1601fc..ccb02888 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit 3a1601fcb254936f6bdfc22e246d2d0fa65eeae7 +Subproject commit ccb02888957ca79243b16f91cb0fcd04decef894 diff --git a/sim/src/main/cc/firesim/firesim_top.cc b/sim/src/main/cc/firesim/firesim_top.cc index 12c09d42..44f35e2e 100644 --- a/sim/src/main/cc/firesim/firesim_top.cc +++ b/sim/src/main/cc/firesim/firesim_top.cc @@ -348,7 +348,7 @@ uint64_t host_mem_offset = -0x80000000LL; bool firesim_top_t::simulation_complete() { bool is_complete = false; - for (auto e: endpoints) { + for (auto &e: endpoints) { is_complete |= e->terminate(); } return is_complete; @@ -362,7 +362,7 @@ uint64_t firesim_top_t::profile_models(){ } int firesim_top_t::exit_code(){ - for (auto e: endpoints) { + for (auto &e: endpoints) { if (e->exit_code()) return e->exit_code(); } @@ -371,11 +371,11 @@ int firesim_top_t::exit_code(){ void firesim_top_t::run() { - for (auto e: fpga_models) { + for (auto &e: fpga_models) { e->init(); } - for (auto e: endpoints) { + for (auto &e: endpoints) { e->init(); } @@ -394,7 +394,7 @@ void firesim_top_t::run() { run_scheduled_tasks(); step(get_largest_stepsize(), false); while(!done() && !simulation_complete()){ - for (auto e: endpoints) e->tick(); + for (auto &e: endpoints) e->tick(); } } diff --git a/sim/src/main/cc/firesim/firesim_top.h b/sim/src/main/cc/firesim/firesim_top.h index 69cd7b4d..f8ef3c14 100644 --- a/sim/src/main/cc/firesim/firesim_top.h +++ b/sim/src/main/cc/firesim/firesim_top.h @@ -1,6 +1,8 @@ #ifndef __FIRESIM_TOP_H #define __FIRESIM_TOP_H +#include + #include "simif.h" #include "endpoints/endpoint.h" #include "endpoints/fpga_model.h" @@ -16,12 +18,12 @@ class firesim_top_t: virtual simif_t, public systematic_scheduler_t protected: void add_endpoint(endpoint_t* endpoint) { - endpoints.push_back(endpoint); + endpoints.push_back(std::unique_ptr(endpoint)); } private: // Memory mapped endpoints bound to software models - std::vector endpoints; + std::vector > endpoints; // FPGA-hosted models with programmable registers & instrumentation std::vector fpga_models; From af6b3f6bf17aa16cb59ba99f5e46e652279834b5 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 12 Dec 2018 02:25:35 -0800 Subject: [PATCH 12/26] [print] Bring up printSynth in rocket --- sim/midas | 2 +- sim/src/main/cc/firesim/firesim_top.cc | 26 +++++++++++++++++++-- sim/src/main/cc/firesim/firesim_top.h | 4 ++++ sim/src/main/scala/firesim/SimConfigs.scala | 1 + 4 files changed, 30 insertions(+), 3 deletions(-) diff --git a/sim/midas b/sim/midas index ccb02888..3a1601fc 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit ccb02888957ca79243b16f91cb0fcd04decef894 +Subproject commit 3a1601fcb254936f6bdfc22e246d2d0fa65eeae7 diff --git a/sim/src/main/cc/firesim/firesim_top.cc b/sim/src/main/cc/firesim/firesim_top.cc index 44f35e2e..f3ec9810 100644 --- a/sim/src/main/cc/firesim/firesim_top.cc +++ b/sim/src/main/cc/firesim/firesim_top.cc @@ -11,6 +11,7 @@ #include "endpoints/sim_mem.h" #include "endpoints/fpga_memory_model.h" #include "endpoints/synthesized_assertions.h" +#include "endpoints/synthesized_prints.h" firesim_top_t::firesim_top_t(int argc, char** argv) { @@ -333,11 +334,29 @@ uint64_t host_mem_offset = -0x80000000LL; #endif #endif - // add more endpoints here +// There can only be one instance of assert and print widgets as their IO is +// uniquely generated by a FIRRTL transform #ifdef ASSERTIONWIDGET_struct_guard #ifdef ASSERTIONWIDGET_0_PRESENT ASSERTIONWIDGET_0_substruct_create; - endpoints.push_back(new synthesized_assertions_t(this, ASSERTIONWIDGET_0_substruct)); + add_endpoint(new synthesized_assertions_t(this, ASSERTIONWIDGET_0_substruct)); + #endif +#endif + +#ifdef PRINTWIDGET_struct_guard + #ifdef PRINTWIDGET_0_PRESENT + PRINTWIDGET_0_substruct_create; + print_endpoint = new synthesized_prints_t(this, + args, + PRINTWIDGET_0_substruct, + PRINTWIDGET_0_print_count, + PRINTWIDGET_0_token_bytes, + PRINTWIDGET_0_print_offsets, + PRINTWIDGET_0_format_strings, + PRINTWIDGET_0_argument_counts, + PRINTWIDGET_0_argument_widths, + PRINTWIDGET_0_DMA_ADDR); + add_endpoint(print_endpoint); #endif #endif // Add functions you'd like to periodically invoke on a paused simulator here. @@ -425,5 +444,8 @@ void firesim_top_t::run() { for (auto e: fpga_models) { e->finish(); } +#ifdef PRINTWIDGET_0_PRESENT + print_endpoint->finish(); +#endif } diff --git a/sim/src/main/cc/firesim/firesim_top.h b/sim/src/main/cc/firesim/firesim_top.h index f8ef3c14..db8afe52 100644 --- a/sim/src/main/cc/firesim/firesim_top.h +++ b/sim/src/main/cc/firesim/firesim_top.h @@ -8,6 +8,8 @@ #include "endpoints/fpga_model.h" #include "systematic_scheduler.h" +#include "endpoints/synthesized_prints.h" + class firesim_top_t: virtual simif_t, public systematic_scheduler_t { public: @@ -27,6 +29,8 @@ class firesim_top_t: virtual simif_t, public systematic_scheduler_t // FPGA-hosted models with programmable registers & instrumentation std::vector fpga_models; + synthesized_prints_t * print_endpoint; + // profile interval: # of cycles to advance before profiling instrumentation registers in models uint64_t profile_interval = -1; uint64_t profile_models(); diff --git a/sim/src/main/scala/firesim/SimConfigs.scala b/sim/src/main/scala/firesim/SimConfigs.scala index dd22ad57..9150ef36 100644 --- a/sim/src/main/scala/firesim/SimConfigs.scala +++ b/sim/src/main/scala/firesim/SimConfigs.scala @@ -33,6 +33,7 @@ class WithSynthAsserts extends Config((site, here, up) => { // Experimental: mixing this in will enable print synthesis class WithPrintSynthesis extends Config((site, here, up) => { + case midas.SynthPrints => true case EndpointKey => EndpointMap(Seq(new midas.widgets.PrintRecordEndpoint)) ++ up(EndpointKey) }) From e57b8dfe73ab997a0a78cfe7feaa2492790f634e Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 12 Dec 2018 22:46:53 +0000 Subject: [PATCH 13/26] [print] Ifdef out the print widget pointer if not used --- sim/src/main/cc/firesim/firesim_top.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sim/src/main/cc/firesim/firesim_top.h b/sim/src/main/cc/firesim/firesim_top.h index db8afe52..c5489054 100644 --- a/sim/src/main/cc/firesim/firesim_top.h +++ b/sim/src/main/cc/firesim/firesim_top.h @@ -29,7 +29,9 @@ class firesim_top_t: virtual simif_t, public systematic_scheduler_t // FPGA-hosted models with programmable registers & instrumentation std::vector fpga_models; +#ifdef PRINTWIDGET_struct_guard synthesized_prints_t * print_endpoint; +#endif // profile interval: # of cycles to advance before profiling instrumentation registers in models uint64_t profile_interval = -1; From 0c0176861182c42a99de1f19d3399b46d3758d78 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 14 Dec 2018 01:04:44 +0000 Subject: [PATCH 14/26] Bump midas --- sim/midas | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/midas b/sim/midas index 3a1601fc..35b0abd4 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit 3a1601fcb254936f6bdfc22e246d2d0fa65eeae7 +Subproject commit 35b0abd462d78e769d8c1e86fecfc30ee409b207 From 364b6aa4274724ae1c83682302780727d5432be8 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 14 Dec 2018 04:55:49 +0000 Subject: [PATCH 15/26] Bump aws-fpga for updated constraints --- platforms/f1/aws-fpga | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platforms/f1/aws-fpga b/platforms/f1/aws-fpga index 50d4a558..71a36109 160000 --- a/platforms/f1/aws-fpga +++ b/platforms/f1/aws-fpga @@ -1 +1 @@ -Subproject commit 50d4a55873741d01f9381f6fa56aa6ced2a4bb5b +Subproject commit 71a361090c98b89455deb5fd90eba8f08b3b34e8 From 30507d49f630ebf881a64fc3ee005c5aea24914a Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 14 Dec 2018 07:06:07 +0000 Subject: [PATCH 16/26] [print] Add a (currently failing) test to diff output --- sim/midas | 2 +- sim/src/main/scala/midasexamples/Config.scala | 1 + .../scala/midasexamples/PrintfModule.scala | 8 ++++---- .../scala/midasexamples/TutorialSuite.scala | 18 +++++++++++++++++- 4 files changed, 23 insertions(+), 6 deletions(-) diff --git a/sim/midas b/sim/midas index 35b0abd4..20ba8223 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit 35b0abd462d78e769d8c1e86fecfc30ee409b207 +Subproject commit 20ba8223fe51712606d4964fc4ba750fef35b3f7 diff --git a/sim/src/main/scala/midasexamples/Config.scala b/sim/src/main/scala/midasexamples/Config.scala index 2e5075f4..6f8718ce 100644 --- a/sim/src/main/scala/midasexamples/Config.scala +++ b/sim/src/main/scala/midasexamples/Config.scala @@ -10,6 +10,7 @@ import junctions._ // This is incomplete and must be mixed into a complete platform config class DefaultMIDASConfig extends Config(new Config((site, here, up) => { case SynthAsserts => true + case SynthPrints => true }) ++ new Config(new firesim.firesim.WithDefaultMemModel)) class PointerChaserConfig extends Config((site, here, up) => { diff --git a/sim/src/main/scala/midasexamples/PrintfModule.scala b/sim/src/main/scala/midasexamples/PrintfModule.scala index 5bb0004c..d54052d5 100644 --- a/sim/src/main/scala/midasexamples/PrintfModule.scala +++ b/sim/src/main/scala/midasexamples/PrintfModule.scala @@ -15,11 +15,11 @@ class PrintfModule extends MultiIOModule { when(a) { cycle := cycle + 1.U } - printf(SynthesizePrintf("A: %d\n", cycle)) - when(b) { printf(SynthesizePrintf("B asserted\n")) } // Argument-less print + printf(SynthesizePrintf("SYNTHESIZED_PRINT A: %d\n", cycle)) + when(b) { printf(SynthesizePrintf("SYNTHESIZED_PRINT B asserted\n")) } // Argument-less print val wideArgument = VecInit(Seq.fill(33)(WireInit(cycle))).asUInt - printf(SynthesizePrintf("wideArgument: %x\n", wideArgument)) // argument width > DMA width + printf(SynthesizePrintf("SYNTHESIZED_PRINT wideArgument: %x\n", wideArgument)) // argument width > DMA width val childInst = Module(new PrintfModuleChild) childInst.c := a @@ -31,7 +31,7 @@ class PrintfModuleChild extends MultiIOModule { val d = IO(Input(UInt(16.W))) when (c ^ d(0) && d > 16.U) { - printf(SynthesizePrintf("C: %b, D: %d\n", c, d)) + printf(SynthesizePrintf("SYNTHESIZED_PRINT C: %b, D: %d\n", c, d)) } } diff --git a/sim/src/test/scala/midasexamples/TutorialSuite.scala b/sim/src/test/scala/midasexamples/TutorialSuite.scala index 18127d64..e5dc1f0a 100644 --- a/sim/src/test/scala/midasexamples/TutorialSuite.scala +++ b/sim/src/test/scala/midasexamples/TutorialSuite.scala @@ -3,6 +3,7 @@ package firesim.midasexamples import java.io.File import scala.sys.process.{stringSeqToProcess, ProcessLogger} +import scala.io.Source abstract class TutorialSuite( val targetName: String, // See GeneratorUtils @@ -90,4 +91,19 @@ class StackF1Test extends TutorialSuite("Stack", midas.F1, 8) class RiscF1Test extends TutorialSuite("Risc", midas.F1, 64) class RiscSRAMF1Test extends TutorialSuite("RiscSRAM", midas.F1, 64) class AssertModuleF1Test extends TutorialSuite("AssertModule", midas.F1) -class PrintfModuleF1Test extends TutorialSuite("PrintfModule", midas.F1) +class PrintfModuleF1Test extends TutorialSuite("PrintfModule", midas.F1, + simulationArgs = Seq("+print-human-readable", "+printfile=synthprinttest.out")) { + + behavior of "synthesized print logs" + it should "match the logs produced by the verilated design" in { + def printLines(filename: File): Seq[String] = { + val lines = Source.fromFile(filename).getLines.toList + lines.filter(_.startsWith("SYNTHESIZED_PRINT")) + } + + val verilatedOutput = printLines(new File(outDir, s"/${targetName}.verilator.out")) + val synthPrintOutput = printLines(new File(genDir, "/synthprinttest.out")) + assert(verilatedOutput.size == synthPrintOutput.size && verilatedOutput.nonEmpty) + } + +} From e7825e7962f6e4d1c75c7a809354ec52cb9f3c0f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 15 Dec 2018 12:14:29 -0800 Subject: [PATCH 17/26] [print] Diff logs in scalatest --- sim/midas | 2 +- sim/src/main/cc/midasexamples/PrintfModule.h | 3 ++ .../scala/midasexamples/PrintfModule.scala | 17 +++++----- .../scala/midasexamples/TutorialSuite.scala | 34 ++++++++++++------- 4 files changed, 34 insertions(+), 22 deletions(-) diff --git a/sim/midas b/sim/midas index 20ba8223..efb32bfd 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit 20ba8223fe51712606d4964fc4ba750fef35b3f7 +Subproject commit efb32bfdc18f4d606a1f1a56dca04eee57edcbaf diff --git a/sim/src/main/cc/midasexamples/PrintfModule.h b/sim/src/main/cc/midasexamples/PrintfModule.h index 3ef9f004..bcdb9c94 100644 --- a/sim/src/main/cc/midasexamples/PrintfModule.h +++ b/sim/src/main/cc/midasexamples/PrintfModule.h @@ -38,6 +38,9 @@ public: while (!done()) { print_endpoint->tick(); } + // Add a couple extra flushes to capture tokens that are collected after done is asserted. + print_endpoint->flush(); + print_endpoint->flush(); print_endpoint->finish(); }; }; diff --git a/sim/src/main/scala/midasexamples/PrintfModule.scala b/sim/src/main/scala/midasexamples/PrintfModule.scala index d54052d5..86e40946 100644 --- a/sim/src/main/scala/midasexamples/PrintfModule.scala +++ b/sim/src/main/scala/midasexamples/PrintfModule.scala @@ -15,23 +15,24 @@ class PrintfModule extends MultiIOModule { when(a) { cycle := cycle + 1.U } - printf(SynthesizePrintf("SYNTHESIZED_PRINT A: %d\n", cycle)) - when(b) { printf(SynthesizePrintf("SYNTHESIZED_PRINT B asserted\n")) } // Argument-less print + // Printf format strings must be prefixed with "SYNTHESIZED_PRINT CYCLE: %d" + // so they can be pulled out of RTL simulators log and sorted within a cycle + // As the printf order will be different betwen RTL simulator and synthesized stream + printf(SynthesizePrintf("SYNTHESIZED_PRINT CYCLE: %d\n", cycle)) val wideArgument = VecInit(Seq.fill(33)(WireInit(cycle))).asUInt - printf(SynthesizePrintf("SYNTHESIZED_PRINT wideArgument: %x\n", wideArgument)) // argument width > DMA width + printf(SynthesizePrintf("SYNTHESIZED_PRINT CYCLE: %d wideArgument: %x\n", cycle, wideArgument)) // argument width > DMA width val childInst = Module(new PrintfModuleChild) childInst.c := a - childInst.d := cycle + childInst.cycle := cycle } class PrintfModuleChild extends MultiIOModule { val c = IO(Input(Bool())) - val d = IO(Input(UInt(16.W))) + val cycle = IO(Input(UInt(16.W))) - when (c ^ d(0) && d > 16.U) { - printf(SynthesizePrintf("SYNTHESIZED_PRINT C: %b, D: %d\n", c, d)) - } + val lfsr = chisel3.util.LFSR16(c) + printf(SynthesizePrintf("SYNTHESIZED_PRINT CYCLE: %d LFSR: %x\n", cycle, lfsr)) } diff --git a/sim/src/test/scala/midasexamples/TutorialSuite.scala b/sim/src/test/scala/midasexamples/TutorialSuite.scala index e5dc1f0a..9ce1fafb 100644 --- a/sim/src/test/scala/midasexamples/TutorialSuite.scala +++ b/sim/src/test/scala/midasexamples/TutorialSuite.scala @@ -70,6 +70,26 @@ abstract class TutorialSuite( ignore should s"pass in ${testEnv}" in { } } } + + // Checks that the synthesized print log in ${genDir}/${synthPrintLog} matches the + // printfs from the RTL simulator + def diffSynthesizedPrints(synthPrintLog: String) { + behavior of "synthesized print log" + it should "match the logs produced by the verilated design" in { + def printLines(filename: File): Seq[String] = { + val lines = Source.fromFile(filename).getLines.toList + lines.filter(_.startsWith("SYNTHESIZED_PRINT")).sorted + } + + val verilatedOutput = printLines(new File(outDir, s"/${targetName}.verilator.out")) + val synthPrintOutput = printLines(new File(genDir, s"/${synthPrintLog}")) + assert(verilatedOutput.size == synthPrintOutput.size && verilatedOutput.nonEmpty) + for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) { + assert(vPrint == sPrint) + } + } + } + clean mkdirs compile @@ -93,17 +113,5 @@ class RiscSRAMF1Test extends TutorialSuite("RiscSRAM", midas.F1, 64) class AssertModuleF1Test extends TutorialSuite("AssertModule", midas.F1) class PrintfModuleF1Test extends TutorialSuite("PrintfModule", midas.F1, simulationArgs = Seq("+print-human-readable", "+printfile=synthprinttest.out")) { - - behavior of "synthesized print logs" - it should "match the logs produced by the verilated design" in { - def printLines(filename: File): Seq[String] = { - val lines = Source.fromFile(filename).getLines.toList - lines.filter(_.startsWith("SYNTHESIZED_PRINT")) - } - - val verilatedOutput = printLines(new File(outDir, s"/${targetName}.verilator.out")) - val synthPrintOutput = printLines(new File(genDir, "/synthprinttest.out")) - assert(verilatedOutput.size == synthPrintOutput.size && verilatedOutput.nonEmpty) - } - + diffSynthesizedPrints("synthprinttest.out") } From 1073f6b75947267de53393f577496ad42480abb0 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 15 Dec 2018 14:06:07 -0800 Subject: [PATCH 18/26] [print] Add a midasexample that packs narrow printf tokens --- sim/midas | 2 +- sim/src/main/cc/midasexamples/Driver.cc | 2 + .../cc/midasexamples/NarrowPrintfModule.h | 15 +++++ sim/src/main/cc/midasexamples/PrintfModule.h | 60 +++++++++++-------- .../scala/midasexamples/PrintfModule.scala | 12 ++++ .../scala/midasexamples/TutorialSuite.scala | 4 ++ 6 files changed, 69 insertions(+), 26 deletions(-) create mode 100644 sim/src/main/cc/midasexamples/NarrowPrintfModule.h diff --git a/sim/midas b/sim/midas index efb32bfd..86dcbfe8 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit efb32bfdc18f4d606a1f1a56dca04eee57edcbaf +Subproject commit 86dcbfe8f2e1e664b2876d413c92b7a7bda8dde4 diff --git a/sim/src/main/cc/midasexamples/Driver.cc b/sim/src/main/cc/midasexamples/Driver.cc index fb820f66..6c3fade7 100644 --- a/sim/src/main/cc/midasexamples/Driver.cc +++ b/sim/src/main/cc/midasexamples/Driver.cc @@ -29,6 +29,8 @@ #include "AssertModule.h" #elif defined DESIGNNAME_PrintfModule #include "PrintfModule.h" +#elif defined DESIGNNAME_NarrowPrintfModule +#include "NarrowPrintfModule.h" #endif class dut_emul_t: diff --git a/sim/src/main/cc/midasexamples/NarrowPrintfModule.h b/sim/src/main/cc/midasexamples/NarrowPrintfModule.h new file mode 100644 index 00000000..59be7294 --- /dev/null +++ b/sim/src/main/cc/midasexamples/NarrowPrintfModule.h @@ -0,0 +1,15 @@ +//See LICENSE for license details. + +#include "PrintfModule.h" +class NarrowPrintfModule_t: public print_module_t, virtual simif_t +{ +public: + NarrowPrintfModule_t(int argc, char** argv): print_module_t(argc, argv) {}; + virtual void run() { + print_endpoint->init(); + poke(reset, 1); + step(1); + poke(reset, 0); + run_and_collect_prints(256); + }; +}; diff --git a/sim/src/main/cc/midasexamples/PrintfModule.h b/sim/src/main/cc/midasexamples/PrintfModule.h index bcdb9c94..38e986a6 100644 --- a/sim/src/main/cc/midasexamples/PrintfModule.h +++ b/sim/src/main/cc/midasexamples/PrintfModule.h @@ -5,25 +5,41 @@ #include "simif.h" #include "endpoints/synthesized_prints.h" -class PrintfModule_t: virtual simif_t +class print_module_t: virtual simif_t +{ + public: + std::unique_ptr print_endpoint; + print_module_t(int argc, char** argv) { + PRINTWIDGET_0_substruct_create; + std::vector args(argv + 1, argv + argc); + print_endpoint = std::unique_ptr(new synthesized_prints_t(this, + args, + PRINTWIDGET_0_substruct, + PRINTWIDGET_0_print_count, + PRINTWIDGET_0_token_bytes, + PRINTWIDGET_0_print_offsets, + PRINTWIDGET_0_format_strings, + PRINTWIDGET_0_argument_counts, + PRINTWIDGET_0_argument_widths, + PRINTWIDGET_0_DMA_ADDR)); + }; + void run_and_collect_prints(int cycles) { + step(cycles, false); + while (!done()) { + print_endpoint->tick(); + } + // Add a couple extra flushes to capture tokens that are collected after done is asserted. + print_endpoint->flush(); + print_endpoint->flush(); + print_endpoint->finish(); + }; +}; + +#ifdef DESIGNNAME_PrintfModule +class PrintfModule_t: public print_module_t, virtual simif_t { public: - std::unique_ptr print_endpoint; - PrintfModule_t(int argc, char** argv) { - PRINTWIDGET_0_substruct_create; - std::vector args(argv + 1, argv + argc); - print_endpoint = std::unique_ptr(new synthesized_prints_t(this, - args, - PRINTWIDGET_0_substruct, - PRINTWIDGET_0_print_count, - PRINTWIDGET_0_token_bytes, - PRINTWIDGET_0_print_offsets, - PRINTWIDGET_0_format_strings, - PRINTWIDGET_0_argument_counts, - PRINTWIDGET_0_argument_widths, - PRINTWIDGET_0_DMA_ADDR)); - }; - + PrintfModule_t(int argc, char** argv): print_module_t(argc, argv) {}; virtual void run() { print_endpoint->init(); poke(reset, 1); @@ -34,13 +50,7 @@ public: step(1); poke(a, 1); poke(b, 1); - step(128, false); - while (!done()) { - print_endpoint->tick(); - } - // Add a couple extra flushes to capture tokens that are collected after done is asserted. - print_endpoint->flush(); - print_endpoint->flush(); - print_endpoint->finish(); + run_and_collect_prints(256); }; }; +#endif //DESIGNNAME_PrintfModule diff --git a/sim/src/main/scala/midasexamples/PrintfModule.scala b/sim/src/main/scala/midasexamples/PrintfModule.scala index 86e40946..4c2610e9 100644 --- a/sim/src/main/scala/midasexamples/PrintfModule.scala +++ b/sim/src/main/scala/midasexamples/PrintfModule.scala @@ -3,6 +3,7 @@ package firesim.midasexamples import chisel3._ +import chisel3.util.LFSR16 import chisel3.experimental.MultiIOModule import midas.targetutils.SynthesizePrintf @@ -34,5 +35,16 @@ class PrintfModuleChild extends MultiIOModule { val lfsr = chisel3.util.LFSR16(c) printf(SynthesizePrintf("SYNTHESIZED_PRINT CYCLE: %d LFSR: %x\n", cycle, lfsr)) + + //when (lsfr(0)) { + // printf(SynthesizePrintf(p"SYNTHESIZED_PRINT CYCLE: ${cycle} LFSR is odd")) + //} } +class NarrowPrintfModule extends MultiIOModule { + val cycle = RegInit(0.U(12.W)) + cycle := cycle + 1.U + when(LFSR16()(0) & LFSR16()(0)) { + printf(SynthesizePrintf("SYNTHESIZED_PRINT CYCLE: %d\n", cycle)) + } +} diff --git a/sim/src/test/scala/midasexamples/TutorialSuite.scala b/sim/src/test/scala/midasexamples/TutorialSuite.scala index 9ce1fafb..174f9f9b 100644 --- a/sim/src/test/scala/midasexamples/TutorialSuite.scala +++ b/sim/src/test/scala/midasexamples/TutorialSuite.scala @@ -115,3 +115,7 @@ class PrintfModuleF1Test extends TutorialSuite("PrintfModule", midas.F1, simulationArgs = Seq("+print-human-readable", "+printfile=synthprinttest.out")) { diffSynthesizedPrints("synthprinttest.out") } +class NarrowPrintfModuleF1Test extends TutorialSuite("NarrowPrintfModule", midas.F1, + simulationArgs = Seq("+print-human-readable", "+printfile=synthprinttest.out")) { + diffSynthesizedPrints("synthprinttest.out") +} From c50dd9ebfcf3813142878de0abfdb796f7395506 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 15 Dec 2018 16:31:55 -0800 Subject: [PATCH 19/26] [Print] Enable token compression --- sim/midas | 2 +- sim/src/main/cc/firesim/firesim_top.cc | 1 + sim/src/main/cc/midasexamples/NarrowPrintfModule.h | 7 +++++++ sim/src/main/cc/midasexamples/PrintfModule.h | 4 +--- sim/src/main/scala/midasexamples/PrintfModule.scala | 5 +++-- 5 files changed, 13 insertions(+), 6 deletions(-) diff --git a/sim/midas b/sim/midas index 86dcbfe8..0dd32c50 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit 86dcbfe8f2e1e664b2876d413c92b7a7bda8dde4 +Subproject commit 0dd32c50133d42b2ecea1a2c1688273ab3db2815 diff --git a/sim/src/main/cc/firesim/firesim_top.cc b/sim/src/main/cc/firesim/firesim_top.cc index f3ec9810..44cb64de 100644 --- a/sim/src/main/cc/firesim/firesim_top.cc +++ b/sim/src/main/cc/firesim/firesim_top.cc @@ -351,6 +351,7 @@ uint64_t host_mem_offset = -0x80000000LL; PRINTWIDGET_0_substruct, PRINTWIDGET_0_print_count, PRINTWIDGET_0_token_bytes, + PRINTWIDGET_0_idle_cycles_mask, PRINTWIDGET_0_print_offsets, PRINTWIDGET_0_format_strings, PRINTWIDGET_0_argument_counts, diff --git a/sim/src/main/cc/midasexamples/NarrowPrintfModule.h b/sim/src/main/cc/midasexamples/NarrowPrintfModule.h index 59be7294..b62922d2 100644 --- a/sim/src/main/cc/midasexamples/NarrowPrintfModule.h +++ b/sim/src/main/cc/midasexamples/NarrowPrintfModule.h @@ -8,8 +8,15 @@ public: virtual void run() { print_endpoint->init(); poke(reset, 1); + poke(enable, 0); step(1); + poke(enable, 1); poke(reset, 0); + step(4); + // Test idle-cycle rollover + poke(enable, 0); + step(256); + poke(enable, 1); run_and_collect_prints(256); }; }; diff --git a/sim/src/main/cc/midasexamples/PrintfModule.h b/sim/src/main/cc/midasexamples/PrintfModule.h index 38e986a6..98143958 100644 --- a/sim/src/main/cc/midasexamples/PrintfModule.h +++ b/sim/src/main/cc/midasexamples/PrintfModule.h @@ -17,6 +17,7 @@ class print_module_t: virtual simif_t PRINTWIDGET_0_substruct, PRINTWIDGET_0_print_count, PRINTWIDGET_0_token_bytes, + PRINTWIDGET_0_idle_cycles_mask, PRINTWIDGET_0_print_offsets, PRINTWIDGET_0_format_strings, PRINTWIDGET_0_argument_counts, @@ -28,9 +29,6 @@ class print_module_t: virtual simif_t while (!done()) { print_endpoint->tick(); } - // Add a couple extra flushes to capture tokens that are collected after done is asserted. - print_endpoint->flush(); - print_endpoint->flush(); print_endpoint->finish(); }; }; diff --git a/sim/src/main/scala/midasexamples/PrintfModule.scala b/sim/src/main/scala/midasexamples/PrintfModule.scala index 4c2610e9..b481c859 100644 --- a/sim/src/main/scala/midasexamples/PrintfModule.scala +++ b/sim/src/main/scala/midasexamples/PrintfModule.scala @@ -42,9 +42,10 @@ class PrintfModuleChild extends MultiIOModule { } class NarrowPrintfModule extends MultiIOModule { + val enable = IO(Input(Bool())) val cycle = RegInit(0.U(12.W)) cycle := cycle + 1.U - when(LFSR16()(0) & LFSR16()(0)) { - printf(SynthesizePrintf("SYNTHESIZED_PRINT CYCLE: %d\n", cycle)) + when(LFSR16()(0) & LFSR16()(0) & enable) { + printf(SynthesizePrintf("SYNTHESIZED_PRINT CYCLE: %d\n", cycle(5,0))) } } From ce909c1fbefd7b0fbf20dcf29c45fb1ac49c1022 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 15 Dec 2018 16:42:58 -0800 Subject: [PATCH 20/26] Bump midas --- sim/midas | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/midas b/sim/midas index 0dd32c50..066d66a0 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit 0dd32c50133d42b2ecea1a2c1688273ab3db2815 +Subproject commit 066d66a001028b3d7bbfbf371e33af60d65494ee From 5595dbb78588523743f78954a663c55bcef1e85d Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 20 Dec 2018 16:26:21 +0000 Subject: [PATCH 21/26] [print] Add cases for the bugs Albert encountered --- sim/midas | 2 +- sim/src/main/scala/midasexamples/PrintfModule.scala | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/sim/midas b/sim/midas index 066d66a0..2bbe3771 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit 066d66a001028b3d7bbfbf371e33af60d65494ee +Subproject commit 2bbe37715962e552371aea6e66a228bd4d809f01 diff --git a/sim/src/main/scala/midasexamples/PrintfModule.scala b/sim/src/main/scala/midasexamples/PrintfModule.scala index b481c859..6b3a91db 100644 --- a/sim/src/main/scala/midasexamples/PrintfModule.scala +++ b/sim/src/main/scala/midasexamples/PrintfModule.scala @@ -27,6 +27,8 @@ class PrintfModule extends MultiIOModule { val childInst = Module(new PrintfModuleChild) childInst.c := a childInst.cycle := cycle + + printf(SynthesizePrintf("thi$!sn+taS/\neName", "SYNTHESIZED_PRINT CYCLE: %d constantArgument: %x\n", cycle, 1.U(8.W))) } class PrintfModuleChild extends MultiIOModule { From 3df039b6ea9b040177ae91b98e0214f8252e761b Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 28 Dec 2018 15:24:11 +0000 Subject: [PATCH 22/26] Bump midas for TopWiringAnno fix --- sim/midas | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/midas b/sim/midas index 2bbe3771..769d5499 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit 2bbe37715962e552371aea6e66a228bd4d809f01 +Subproject commit 769d549989496326cdda130e4a8585d8f504b542 From 1511828f01bc8b1f494a3571a97704be4affeafe Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 15 Jan 2019 17:32:19 +0000 Subject: [PATCH 23/26] Bump midas --- sim/midas | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/midas b/sim/midas index 769d5499..12991c62 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit 769d549989496326cdda130e4a8585d8f504b542 +Subproject commit 12991c628ce506cf462e5c5c24688bd99c5b2b74 From af1ee60d96747992cd5e5328e9c0755a3bda0fc3 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 15 Jan 2019 17:32:44 +0000 Subject: [PATCH 24/26] Regenerate AGFIS --- .../sample-backup-configs/sample_config_hwdb.ini | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/deploy/sample-backup-configs/sample_config_hwdb.ini b/deploy/sample-backup-configs/sample_config_hwdb.ini index 4ef9d8bc..efac87ef 100644 --- a/deploy/sample-backup-configs/sample_config_hwdb.ini +++ b/deploy/sample-backup-configs/sample_config_hwdb.ini @@ -10,31 +10,32 @@ # own images. [fireboom-singlecore-nic-ddr3-llc4mb] -agfi=agfi-05c7620b62b901690 +agfi=agfi-00857d0de5aa1d7b7 deploytripletoverride=None customruntimeconfig=None [fireboom-singlecore-no-nic-ddr3-llc4mb] -agfi=agfi-07f3c2762e4349327 +agfi=agfi-0659b86373011fe04 deploytripletoverride=None customruntimeconfig=None [firesim-quadcore-nic-ddr3-llc4mb] -agfi=agfi-0c078780eadb4203b +agfi=agfi-0b929d88d9f66c9f5 deploytripletoverride=None customruntimeconfig=None [firesim-quadcore-no-nic-ddr3-llc4mb] -agfi=agfi-0e9945a181069cc67 +agfi=agfi-0fb7f0fe1602f9cd9 deploytripletoverride=None customruntimeconfig=None [firesim-singlecore-no-nic-lbp] -agfi=agfi-05ca0d174e131e124 +agfi=agfi-047644ef3f61ae041 deploytripletoverride=None customruntimeconfig=None -[firesim-supernode-quadcore-nic-ddr3-llc4mb] -agfi=agfi-012e0df3c4b90375d +[firesim-supernode-singlecore-nic-lbp] +agfi=agfi-0498cf07932fd2e99 deploytripletoverride=None customruntimeconfig=None + From 0afd15372dc3c62f79f8eb6e687b0cf4b23ef59e Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 15 Jan 2019 18:38:57 +0000 Subject: [PATCH 25/26] [printf] Be consistent on user facing names PrintSynthesis -> PrintfSynthesis --- sim/src/main/scala/firesim/SimConfigs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/src/main/scala/firesim/SimConfigs.scala b/sim/src/main/scala/firesim/SimConfigs.scala index 9150ef36..a0148113 100644 --- a/sim/src/main/scala/firesim/SimConfigs.scala +++ b/sim/src/main/scala/firesim/SimConfigs.scala @@ -32,7 +32,7 @@ class WithSynthAsserts extends Config((site, here, up) => { }) // Experimental: mixing this in will enable print synthesis -class WithPrintSynthesis extends Config((site, here, up) => { +class WithPrintfSynthesis extends Config((site, here, up) => { case midas.SynthPrints => true case EndpointKey => EndpointMap(Seq(new midas.widgets.PrintRecordEndpoint)) ++ up(EndpointKey) }) From b6ffeb97e322a36bdfdaa54791c03297b5ab5364 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 15 Jan 2019 10:43:17 -0800 Subject: [PATCH 26/26] [printfs] Add docs --- docs/Advanced-Usage/Debugging/index.rst | 1 + .../Debugging/printf-synthesis.rst | 66 +++++++++++++++++++ 2 files changed, 67 insertions(+) create mode 100644 docs/Advanced-Usage/Debugging/printf-synthesis.rst diff --git a/docs/Advanced-Usage/Debugging/index.rst b/docs/Advanced-Usage/Debugging/index.rst index 2bcbb8a1..72f9852a 100644 --- a/docs/Advanced-Usage/Debugging/index.rst +++ b/docs/Advanced-Usage/Debugging/index.rst @@ -12,3 +12,4 @@ This section describes methods of debugging the target design and the simulation Debugging-Hardware-Using-ILA.rst TracerV.rst DESSERT.rst + printf-synthesis.rst diff --git a/docs/Advanced-Usage/Debugging/printf-synthesis.rst b/docs/Advanced-Usage/Debugging/printf-synthesis.rst new file mode 100644 index 00000000..6379421b --- /dev/null +++ b/docs/Advanced-Usage/Debugging/printf-synthesis.rst @@ -0,0 +1,66 @@ +Printf Synthesis +=================== + +MIDAS can synthesize printfs present in FIRRTL (implemented as ``printf`` +statements) that would otherwise be lost in the FPGA synthesis flow. Rocket and +BOOM have printfs of their commit logs and other useful transaction +streams. + +:: + + C0: 409 [1] pc=[008000004c] W[r10=0000000000000000][1] R[r 0=0000000000000000] R[r20=0000000000000003] inst=[f1402573] csrr a0, mhartid + C0: 410 [0] pc=[008000004c] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r20=0000000000000003] inst=[f1402573] csrr a0, mhartid + C0: 411 [0] pc=[008000004c] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r20=0000000000000003] inst=[f1402573] csrr a0, mhartid + C0: 412 [1] pc=[0080000050] W[r 0=0000000000000000][0] R[r10=0000000000000000] R[r 0=0000000000000000] inst=[00051063] bnez a0, pc + 0 + C0: 413 [1] pc=[0080000054] W[r 5=0000000080000054][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[00000297] auipc t0, 0x0 + C0: 414 [1] pc=[0080000058] W[r 5=0000000080000064][1] R[r 5=0000000080000054] R[r16=0000000000000003] inst=[01028293] addi t0, t0, 16 + C0: 415 [1] pc=[008000005c] W[r 0=0000000000010000][1] R[r 5=0000000080000064] R[r 5=0000000080000064] inst=[30529073] csrw mtvec, t0 + +Synthesizing these printfs lets you capture the same logs on a running FireSim instance. + +Enabling Printf Synthesis +---------------------------- + +To synthesize a printf, in your Chisel source you need to annotate the specific +printfs you'd like to capture. Presently, due to a limitation in Chisel and +FIRRTL's annotation system, you need to annotate the arguments to the printf, not the printf itself, +like so: + +:: + + printf(midas.targetutils.SynthesizePrintf("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata)) + +Be judicious, as synthesizing many, frequently active printfs, will slow down your simulator. + +Once your printfs have been annotated, to enable printf synthesis add the ``WithPrintfSynthesis`` Config to your +PLATFORM_CONFIG in SimConfigs.scala. During compilation, MIDAS will print the +number of printfs it's synthesized. In the target's generated header +(``-const.h``), you'll find metadata for each of the printfs MIDAS synthesized. +This is passed as argument to the constructor of the ``synthesized_prints_t`` +endpoint driver, which will be automatically instantiated in FireSim driver. + +Runtime Arguments +----------------- +**+printfile** + Specifies the file into which the synthesized printf log should written. + +**+print-start** + Specifies the target-cycle at which the printf trace should be captured in the + simulator. Since capturing high-bandwidth printf traces will slow down + simulation, this allows the user to reach the region-of-interest at full simulation speed. + +**+print-end** + Specifies the target cycle at which to stop pulling the synthesized print + trace from the simulator. + +**+print-human-readable** + By default, a captured printf trace will be written to file as a raw, + unformatted binary, as properly formatting the printf further slows the + simulator. Setting this will properly format the print data before writing + it to file. + +Related Publications +-------------------- + +Printf synthesis was first presented in our FPL2018 paper, `DESSERT +`_.