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Update sim/midas/src/main/scala/midas/stage/GoldenGateCompilerPhase.scala 

Co-authored-by: David Biancolin <david.biancolin@sifive.com>
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Russell Horvath 2022-11-14 09:36:51 -08:00 committed by GitHub
parent f9fdcaf6e7
commit 4ba273a272
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sim/midas/src/main/scala/midas/stage/GoldenGateCompilerPhase.scala
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@ -54,7 +54,7 @@ class GoldenGateCompilerPhase extends Phase {
// Note: the final lowering to Verilog is broken up into multiple firrtl.Compiler steps
// to avoid breakages that can emerge from "legal" but unsound pass orderings
// due to understpecified pass constraints + invalidations
// due to underspecified pass constraints + invalidations
// Shunt ILA passes to a seperate compiler to avoid invalidating downstream steps
val loweringCompiler = new Compiler(
targets = Seq(