From 4ba273a2721aadcd6c518c672605cf1a81e82ad5 Mon Sep 17 00:00:00 2001 From: Russell Horvath <107954876+russell-horvath@users.noreply.github.com> Date: Mon, 14 Nov 2022 09:36:51 -0800 Subject: [PATCH] Update sim/midas/src/main/scala/midas/stage/GoldenGateCompilerPhase.scala Co-authored-by: David Biancolin --- .../src/main/scala/midas/stage/GoldenGateCompilerPhase.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/midas/src/main/scala/midas/stage/GoldenGateCompilerPhase.scala b/sim/midas/src/main/scala/midas/stage/GoldenGateCompilerPhase.scala index 3cc7b358..40978ead 100644 --- a/sim/midas/src/main/scala/midas/stage/GoldenGateCompilerPhase.scala +++ b/sim/midas/src/main/scala/midas/stage/GoldenGateCompilerPhase.scala @@ -54,7 +54,7 @@ class GoldenGateCompilerPhase extends Phase { // Note: the final lowering to Verilog is broken up into multiple firrtl.Compiler steps // to avoid breakages that can emerge from "legal" but unsound pass orderings - // due to understpecified pass constraints + invalidations + // due to underspecified pass constraints + invalidations // Shunt ILA passes to a seperate compiler to avoid invalidating downstream steps val loweringCompiler = new Compiler( targets = Seq(