Merge remote-tracking branch 'origin/main' into revamp-wide-tracerv-w-fix
This commit is contained in:
abejgonzalez
commit
48f1aabe75
|
|
@ -5,7 +5,8 @@ runs:
|
|||
using: "composite"
|
||||
steps:
|
||||
- run: |
|
||||
source /etc/profile.d/conda.sh
|
||||
source /opt/conda/etc/profile.d/conda.sh
|
||||
conda activate firesim
|
||||
./build-setup.sh --skip-validate
|
||||
# All actions that run in a GH-hosted container source env.sh before
|
||||
# running their jobs. This ensures conda is in the runner's path, which
|
||||
|
|
|
|||
|
|
@ -11,13 +11,13 @@ import argparse
|
|||
|
||||
from ci_variables import ci_env
|
||||
|
||||
from typing import List
|
||||
from typing import List, Tuple
|
||||
|
||||
GH_REPO = 'firesim-public-bitstreams'
|
||||
GH_ORG = 'firesim'
|
||||
URL_PREFIX = f"https://raw.githubusercontent.com/{GH_ORG}/{GH_REPO}"
|
||||
|
||||
build_location = "/scratch/buildbot/fstmp"
|
||||
shared_build_dir = "/scratch/buildbot/FIRESIM_BUILD_DIR"
|
||||
|
||||
# taken from https://stackoverflow.com/questions/63427607/python-upload-files-directly-to-github-using-pygithub
|
||||
# IMPORTANT: only works for binary files! (i.e. tar.gz files)
|
||||
|
|
@ -90,6 +90,8 @@ def run_local_buildbitstreams():
|
|||
def modify_config_build(hwdb_entries_to_gen: List[str]) -> str:
|
||||
build_yaml = f"{manager_fsim_dir}/deploy/config_build.yaml"
|
||||
copy_build_yaml = f"{manager_fsim_dir}/deploy/config_build_{hash(tuple(hwdb_entries_to_gen))}.yaml"
|
||||
|
||||
# comment out old lines
|
||||
build_yaml_lines = open(build_yaml).read().split("\n")
|
||||
with open(copy_build_yaml, "w") as byf:
|
||||
for line in build_yaml_lines:
|
||||
|
|
@ -97,15 +99,25 @@ def run_local_buildbitstreams():
|
|||
# comment out AWS specific lines
|
||||
byf.write("# " + line + '\n')
|
||||
elif 'default_build_dir:' in line:
|
||||
byf.write(line.replace('null', build_location) + '\n')
|
||||
elif len([True for hwdb_entry_to_gen in hwdb_entries_to_gen if (f"- {hwdb_entry_to_gen}" in line)]):
|
||||
# remove comment
|
||||
byf.write(line.replace("# ", '') + '\n')
|
||||
byf.write(line.replace('null', shared_build_dir) + '\n')
|
||||
else:
|
||||
byf.write(line + '\n')
|
||||
|
||||
# add new builds to run
|
||||
build_yaml_lines = open(copy_build_yaml).read().split("\n")
|
||||
with open(copy_build_yaml, "w") as byf:
|
||||
for line in build_yaml_lines:
|
||||
if "builds_to_run:" in line and not "#" in line:
|
||||
byf.write(line + '\n')
|
||||
start_space_idx = line.index('b')
|
||||
for hwdb_to_gen in hwdb_entries_to_gen:
|
||||
byf.write((' ' * (start_space_idx + 4)) + f"- {hwdb_to_gen}" + '\n')
|
||||
else:
|
||||
byf.write(line + '\n')
|
||||
|
||||
return copy_build_yaml
|
||||
|
||||
def add_host_list(build_yaml: str, hostlist: List[str]) -> str:
|
||||
def add_host_list(build_yaml: str, hostlist: List[Tuple[str, bool, str]]) -> str:
|
||||
copy_build_yaml = f"{manager_fsim_dir}/deploy/config_build_{hash(tuple(hostlist))}.yaml"
|
||||
build_yaml_lines = open(build_yaml).read().split("\n")
|
||||
with open(copy_build_yaml, "w") as byf:
|
||||
|
|
@ -113,7 +125,11 @@ def run_local_buildbitstreams():
|
|||
if "build_farm_hosts:" in line and not "#" in line:
|
||||
byf.write(line + '\n')
|
||||
start_space_idx = line.index('b')
|
||||
for host in hostlist:
|
||||
for host, use_unique, unique_build_dir in hostlist:
|
||||
if use_unique:
|
||||
byf.write((' ' * (start_space_idx + 4)) + f"- {host}:" + '\n')
|
||||
byf.write((' ' * (start_space_idx + 8)) + f"override_build_dir: {unique_build_dir}" + '\n')
|
||||
else:
|
||||
byf.write((' ' * (start_space_idx + 4)) + f"- {host}" + '\n')
|
||||
elif '- localhost' in line and not '#' in line:
|
||||
byf.write("# " + line + '\n')
|
||||
|
|
@ -204,25 +220,30 @@ def run_local_buildbitstreams():
|
|||
sample_hwdb_file.write(content)
|
||||
sample_hwdb_file.truncate()
|
||||
|
||||
# could potentially use knight/ferry in the future (currently unused since they are currently overloaded)
|
||||
hosts = {
|
||||
("localhost", "vitis:2022.1"),
|
||||
("jktgz", "vivado:2021.1"),
|
||||
("jktqos", "vivado:2021.1"),
|
||||
("firesim1", "vivado:2019.1"),
|
||||
}
|
||||
# priority == roughly the more powerful and available
|
||||
# ipaddr, buildtool:version, use unique build dir, unique build dir path, priority (0 is highest)(unused by code but used to track which machine has most resources)
|
||||
hosts = [
|
||||
("buildbot1@a17", "vitis:2022.1", True, "/scratch/buildbot1/FIRESIM_BUILD_DIR", 0),
|
||||
( "harp", "vitis:2022.1", False, "", 2),
|
||||
("buildbot2@a17", "vitis:2021.1", True, "/scratch/buildbot2/FIRESIM_BUILD_DIR", 0),
|
||||
("buildbot3@a17", "vitis:2021.1", True, "/scratch/buildbot3/FIRESIM_BUILD_DIR", 0),
|
||||
("buildbot4@a17", "vitis:2021.1", True, "/scratch/buildbot4/FIRESIM_BUILD_DIR", 0),
|
||||
( "firesim1", "vitis:2021.1", False, "", 1),
|
||||
( "jktgz", "vivado:2023.1", False, "", 3),
|
||||
( "jktqos", "vivado:2023.1", False, "", 3),
|
||||
]
|
||||
|
||||
def do_builds(batch_hwdbs):
|
||||
assert len(hosts) >= len(batch_hwdbs), f"Need at least {len(batch_hwdbs)} hosts to run builds"
|
||||
|
||||
# map hwdb tuple to hosts
|
||||
hwdb_2_host = {}
|
||||
for hwdb in batch_hwdbs:
|
||||
buildtool_version = hwdb[2]
|
||||
for host in hosts:
|
||||
if host[1] == buildtool_version:
|
||||
if not host[0] in hwdb_2_host.values():
|
||||
hwdb_2_host[hwdb[0]] = host[0]
|
||||
for hwdb, platform, buildtool_version in batch_hwdbs:
|
||||
for host_name, host_buildtool_version, host_use_unique, host_unique_build_dir, host_prio in hosts:
|
||||
if host_buildtool_version == buildtool_version:
|
||||
if not host_name in [h[0] for h in hwdb_2_host.values()]:
|
||||
hwdb_2_host[hwdb] = (host_name, host_use_unique, host_unique_build_dir)
|
||||
break
|
||||
|
||||
assert len(hwdb_2_host) == len(batch_hwdbs), "Unable to map hosts to hwdb build"
|
||||
|
||||
|
|
@ -242,24 +263,31 @@ def run_local_buildbitstreams():
|
|||
replace_in_hwdb(hwdb, link)
|
||||
|
||||
# wipe old data
|
||||
for host in hosts_ordered:
|
||||
run(f"ssh {host} rm -rf {build_location}")
|
||||
for host_name, host_use_unique, host_unique_build_dir in hosts_ordered:
|
||||
if host_use_unique:
|
||||
run(f"ssh {host_name} rm -rf {host_unique_build_dir}")
|
||||
else:
|
||||
run(f"ssh {host_name} rm -rf {shared_build_dir}")
|
||||
|
||||
# note: next two statements can be duplicated to run different builds in phases
|
||||
# i.e. run 4 agfis in 1st phase, then 6 in next
|
||||
|
||||
# order of following list roughly corresponds to build host to use.
|
||||
# i.e. if 1st hwdb in list wants a host with V0 of tools, it will get the 1st host with V0 of tools
|
||||
# in the hosts list
|
||||
|
||||
# same order as in config_build.yaml
|
||||
# hwdb_entry_name, platform_name, buildtool:version
|
||||
batch_hwdbs_in = [
|
||||
("vitis_firesim_rocket_singlecore_no_nic", "vitis", "vitis:2022.1"),
|
||||
("alveo_u250_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u250", "vivado:2021.1"),
|
||||
("alveo_u250_firesim_gemmini_rocket_singlecore_no_nic", "xilinx_alveo_u250", "vivado:2021.1"),
|
||||
]
|
||||
|
||||
do_builds(batch_hwdbs_in)
|
||||
|
||||
batch_hwdbs_in = [
|
||||
("nitefury_firesim_rocket_singlecore_no_nic", "rhsresearch_nitefury_ii", "vitis:2022.1"),
|
||||
("alveo_u200_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u200", "vivado:2021.1"),
|
||||
("alveo_u280_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u280", "vivado:2021.1"),
|
||||
("xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic", "xilinx_vcu118", "vivado:2019.1"),
|
||||
|
||||
("alveo_u250_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u250", "vitis:2021.1"),
|
||||
("alveo_u250_firesim_gemmini_rocket_singlecore_no_nic", "xilinx_alveo_u250", "vitis:2021.1"),
|
||||
("alveo_u200_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u200", "vitis:2021.1"),
|
||||
("alveo_u280_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u280", "vitis:2021.1"),
|
||||
|
||||
("xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic", "xilinx_vcu118", "vivado:2023.1"),
|
||||
]
|
||||
|
||||
do_builds(batch_hwdbs_in)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,56 @@
|
|||
{
|
||||
"categories": [
|
||||
{
|
||||
"title": "## Added",
|
||||
"labels": ["changelog:added"]
|
||||
},
|
||||
{
|
||||
"title": "## Changed",
|
||||
"labels": ["changelog:changed"]
|
||||
},
|
||||
{
|
||||
"title": "## Fixed",
|
||||
"labels": ["changelog:fixed"]
|
||||
},
|
||||
{
|
||||
"title": "## Removed",
|
||||
"labels": ["changelog:removed"]
|
||||
},
|
||||
{
|
||||
"title": "## Uncategorized",
|
||||
"labels": []
|
||||
}
|
||||
],
|
||||
"ignore_labels": [
|
||||
"changelog:omit"
|
||||
],
|
||||
"sort": {
|
||||
"order": "ASC",
|
||||
"on_property": "mergedAt"
|
||||
},
|
||||
"template": "${{CHANGELOG}}\n\n**Full Changelog:** ${{RELEASE_DIFF}}\n",
|
||||
"pr_template": "- ${{TITLE}} (by @${{AUTHOR}} in ${{URL}})${{RELEASE_NOTES}}",
|
||||
"empty_template": "- no changes",
|
||||
"transformers": [
|
||||
{
|
||||
"pattern": "<!--.*-->",
|
||||
"flags": "gus",
|
||||
"target": ""
|
||||
}
|
||||
],
|
||||
"custom_placeholders": [
|
||||
{
|
||||
"name": "RELEASE_NOTES",
|
||||
"source": "BODY",
|
||||
"transformer": {
|
||||
"pattern": ".*#### Release Notes(?:[\n\\s]|(?:<!--.*?-->))*((?:\\S(?!!--)).*?)[\n\\s]*\n#.*",
|
||||
"flags": "gus",
|
||||
"target": "\n $1"
|
||||
}
|
||||
}
|
||||
],
|
||||
"trim_values": false,
|
||||
"max_tags_to_fetch": 200,
|
||||
"max_pull_requests": 500,
|
||||
"max_back_track_time_days": 365
|
||||
}
|
||||
|
|
@ -11,9 +11,11 @@ defaults:
|
|||
env:
|
||||
PERSONAL_ACCESS_TOKEN: ${{ secrets.BARTENDER_PERSONAL_ACCESS_TOKEN }}
|
||||
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
|
||||
AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID }}
|
||||
AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY }}
|
||||
AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION }}
|
||||
AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID_08012023 }}
|
||||
AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY_08012023 }}
|
||||
AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION_08012023 }}
|
||||
FIRESIM_PEM: ${{ secrets.FIRESIM_PEM_08012023 }}
|
||||
FIRESIM_PEM_PUBLIC: ${{ secrets.FIRESIM_PEM_PUBLIC }}
|
||||
AZURE_CLIENT_ID: ${{ secrets.AZURE_CLIENT_ID }}
|
||||
AZURE_CLIENT_SECRET: ${{ secrets.AZURE_CLIENT_SECRET }}
|
||||
AZURE_TENANT_ID: ${{ secrets.AZURE_TENANT_ID }}
|
||||
|
|
@ -22,8 +24,6 @@ env:
|
|||
AZURE_RESOURCE_GROUP: ${{ secrets.AZURE_RESOURCE_GROUP }}
|
||||
AZURE_CI_SUBNET_ID : ${{ secrets.AZURE_CI_SUBNET_ID }}
|
||||
AZURE_CI_NSG_ID : ${{ secrets.AZURE_CI_NSG_ID }}
|
||||
FIRESIM_PEM: ${{ secrets.FIRESIM_PEM }}
|
||||
FIRESIM_PEM_PUBLIC: ${{ secrets.FIRESIM_PEM_PUBLIC }}
|
||||
MANAGER_FIRESIM_LOCATION: "~/firesim"
|
||||
REMOTE_WORK_DIR: unused
|
||||
TERM: xterm-256-color
|
||||
|
|
|
|||
|
|
@ -20,10 +20,10 @@ defaults:
|
|||
|
||||
env:
|
||||
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
|
||||
AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID }}
|
||||
AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY }}
|
||||
AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION }}
|
||||
FIRESIM_PEM: ${{ secrets.FIRESIM_PEM }}
|
||||
AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID_08012023 }}
|
||||
AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY_08012023 }}
|
||||
AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION_08012023 }}
|
||||
FIRESIM_PEM: ${{ secrets.FIRESIM_PEM_08012023 }}
|
||||
FIRESIM-REPO-DEP-KEY: ${{ secrets.BARTENDER_PRIVATE_SSH_KEY }}
|
||||
MANAGER_FIRESIM_LOCATION: "~/firesim"
|
||||
LANG: "en_US.UTF-8" # required by SBT when it sees boost directories
|
||||
|
|
@ -53,16 +53,7 @@ jobs:
|
|||
needs: change-filters
|
||||
if: needs.change-filters.outputs.needs-scala-doc == 'true'
|
||||
runs-on: ubuntu-20.04
|
||||
container:
|
||||
image: firesim/firesim-ci:v1.3
|
||||
options: --entrypoint /bin/bash
|
||||
env:
|
||||
JAVA_HEAP_SIZE: 3500M # Default JVM maximum heap limit
|
||||
steps:
|
||||
- run: |
|
||||
sudo yum -y remove git git224 git224-core ius-release.noarch # remove any older git versions and collateral first from docker image
|
||||
sudo yum -y install https://repo.ius.io/ius-release-el7.rpm # re-install for now
|
||||
sudo yum -y install git236 # install working git version (must match machine-launch)
|
||||
- uses: actions/checkout@v3
|
||||
- uses: ./.github/actions/repo-setup
|
||||
- uses: ./.github/actions/build-scala-doc
|
||||
|
|
|
|||
|
|
@ -14,9 +14,11 @@ defaults:
|
|||
env:
|
||||
PERSONAL_ACCESS_TOKEN: ${{ secrets.BARTENDER_PERSONAL_ACCESS_TOKEN }}
|
||||
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
|
||||
AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID }}
|
||||
AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY }}
|
||||
AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION }}
|
||||
AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID_08012023 }}
|
||||
AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY_08012023 }}
|
||||
AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION_08012023 }}
|
||||
FIRESIM_PEM: ${{ secrets.FIRESIM_PEM_08012023 }}
|
||||
FIRESIM_PEM_PUBLIC: ${{ secrets.FIRESIM_PEM_PUBLIC }}
|
||||
AZURE_CLIENT_ID: ${{ secrets.AZURE_CLIENT_ID }}
|
||||
AZURE_CLIENT_SECRET: ${{ secrets.AZURE_CLIENT_SECRET }}
|
||||
AZURE_TENANT_ID: ${{ secrets.AZURE_TENANT_ID }}
|
||||
|
|
@ -25,8 +27,6 @@ env:
|
|||
AZURE_RESOURCE_GROUP: ${{ secrets.AZURE_RESOURCE_GROUP }}
|
||||
AZURE_CI_SUBNET_ID : ${{ secrets.AZURE_CI_SUBNET_ID }}
|
||||
AZURE_CI_NSG_ID : ${{ secrets.AZURE_CI_NSG_ID }}
|
||||
FIRESIM_PEM: ${{ secrets.FIRESIM_PEM }}
|
||||
FIRESIM_PEM_PUBLIC: ${{ secrets.FIRESIM_PEM_PUBLIC }}
|
||||
MANAGER_FIRESIM_LOCATION: "~/firesim"
|
||||
LANG: "en_US.UTF-8" # required by SBT when it sees boost directories
|
||||
LANGUAGE: "en_US:en"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
# adapted from https://github.com/chipsalliance/chisel/blob/main/.github/workflows/release-notes.yml
|
||||
|
||||
name: Generate Release Notes
|
||||
|
||||
on:
|
||||
release:
|
||||
types: [created]
|
||||
workflow_dispatch:
|
||||
inputs:
|
||||
toTag:
|
||||
description: 'Tag or ref for which to generate release notes'
|
||||
required: true
|
||||
fromTag:
|
||||
# If you leave this blank, it'll select previous SemVer version
|
||||
# WARNING: Cannot use anything older than a005498 because of the git tree merge
|
||||
description: 'Tag or ref from which to start generating release notes'
|
||||
required: false
|
||||
|
||||
|
||||
jobs:
|
||||
generate_release_notes:
|
||||
name: Generate Release Notes
|
||||
runs-on: ubuntu-latest
|
||||
|
||||
steps:
|
||||
- name: Checkout
|
||||
uses: actions/checkout@v3
|
||||
- name: Build Release Notes
|
||||
id: release-notes
|
||||
uses: mikepenz/release-changelog-builder-action@v3.7.0
|
||||
with:
|
||||
configuration: .github/workflows/config/release-notes.json
|
||||
failOnError: true
|
||||
# Amazingly, on release where the inputs are empty, this just does the right thing
|
||||
# The "toTag" is the released tag, and the "fromTag" is the previous tag according to SemVer
|
||||
fromTag: ${{ github.event.inputs.fromTag }}
|
||||
toTag: ${{ github.event.inputs.toTag }}
|
||||
token: ${{ secrets.GITHUB_TOKEN }}
|
||||
- name: Report Release Notes
|
||||
# Put output through env variable to make it robust to quotes
|
||||
env:
|
||||
CHANGELOG: ${{steps.release-notes.outputs.changelog}}
|
||||
run: echo "$CHANGELOG" >> $GITHUB_STEP_SUMMARY
|
||||
- name: Upload Release Notes (on release)
|
||||
if: github.event_name == 'release'
|
||||
uses: softprops/action-gh-release@v0.1.15
|
||||
with:
|
||||
body: ${{ steps.release-notes.outputs.changelog }}
|
||||
- name: Error on uncategorized PRs
|
||||
if: steps.release-notes.outputs.uncategorized_prs != 0
|
||||
run: exit 1
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
# adapted from https://github.com/chipsalliance/chisel/blob/main/.github/workflows/require-label.yml
|
||||
|
||||
name: Require Release Notes Label
|
||||
|
||||
on:
|
||||
pull_request:
|
||||
branches:
|
||||
- main
|
||||
types:
|
||||
- opened
|
||||
- synchronize
|
||||
- reopened
|
||||
- labeled
|
||||
- unlabeled
|
||||
|
||||
jobs:
|
||||
check_labels:
|
||||
name: Check Labels
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- uses: docker://agilepathway/pull-request-label-checker:v1.4.25
|
||||
with:
|
||||
one_of: changelog:added,changelog:changed,changelog:fixed,changelog:omit,changelog:removed
|
||||
repo_token: ${{ secrets.GITHUB_TOKEN }}
|
||||
17
CHANGELOG.md
17
CHANGELOG.md
|
|
@ -2,6 +2,23 @@
|
|||
|
||||
This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/
|
||||
|
||||
## [1.17.1] - 2023-07-14
|
||||
Fix missing mcs file in VCU118 bitstream_tar. Automatically generate release notes for faster releases. CI improvements.
|
||||
|
||||
### Added
|
||||
- Bucket log docs (by @joey0320 in https://github.com/firesim/firesim/pull/1575)
|
||||
- Add release note automation (by @abejgonzalez in https://github.com/firesim/firesim/pull/1595)
|
||||
|
||||
### Changed
|
||||
- Use bar-tender specific access (by @abejgonzalez in https://github.com/firesim/firesim/pull/1558)
|
||||
- CI modifications - Support Vivado 2022.1, New CI machine(s) (by @abejgonzalez in https://github.com/firesim/firesim/pull/1592)
|
||||
|
||||
### Fixed
|
||||
- Fix VCU118 bitstream_tar missing mcs file (by @abejgonzalez in https://github.com/firesim/firesim/pull/1592)
|
||||
- Additional VCU118 initial setup fixes (by @sagark in https://github.com/firesim/firesim/pull/1606)
|
||||
|
||||
**Full Changelog:** https://github.com/firesim/firesim/compare/1.17.0...main
|
||||
|
||||
## [1.17.0] - 2023-06-16
|
||||
Support for several new local FPGA boards added: Xilinx VCU118 (w/XDMA), Xilinx Alveo U250/U280 (w/XDMA, in addition to previous Vitis support), RHSResearch NiteFury II (w/XDMA). FireSim now also supports Xcelium for metasims.
|
||||
|
||||
|
|
|
|||
|
|
@ -142,7 +142,7 @@ else
|
|||
./scripts/generate-conda-lockfile.sh
|
||||
fi
|
||||
LOCKFILE="$(find $RDIR/conda-reqs/*.conda-lock.yml)"
|
||||
conda-lock install -p $RDIR/.conda-env $LOCKFILE
|
||||
conda-lock install --conda $(which conda) -p $RDIR/.conda-env $LOCKFILE
|
||||
source $RDIR/.conda-env/etc/profile.d/conda.sh
|
||||
conda activate $RDIR/.conda-env
|
||||
env_append "$CONDA_ACTIVATE_PREAMBLE"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -23,8 +23,8 @@ dependencies:
|
|||
# bundle FireSim driver with deps into installer shell-script
|
||||
- constructor
|
||||
|
||||
- gcc
|
||||
- gxx
|
||||
- gcc<13
|
||||
- gxx<13
|
||||
- sysroot_linux-64=2.17 # needed to match pre-built CI XRT glibc version
|
||||
- conda-gcc-specs
|
||||
- binutils
|
||||
|
|
@ -88,6 +88,7 @@ dependencies:
|
|||
- elfutils
|
||||
- libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock
|
||||
- conda-lock=1.4
|
||||
- autoconf
|
||||
|
||||
# clang-format for driver coding style enforcement.
|
||||
- clang-format
|
||||
|
|
|
|||
|
|
@ -685,6 +685,7 @@ class XilinxAlveoBitBuilder(BitBuilder):
|
|||
local_cl_dir = f"{local_results_dir}/{fpga_build_postfix}"
|
||||
bit_path = f"{local_cl_dir}/vivado_proj/firesim.bit"
|
||||
mcs_path = f"{local_cl_dir}/vivado_proj/firesim.mcs"
|
||||
mcs_secondary_path = f"{local_cl_dir}/vivado_proj/firesim_secondary.mcs"
|
||||
tar_staging_path = f"{local_cl_dir}/{self.build_config.PLATFORM}"
|
||||
tar_name = "firesim.tar.gz"
|
||||
|
||||
|
|
@ -694,8 +695,9 @@ class XilinxAlveoBitBuilder(BitBuilder):
|
|||
|
||||
# store bitfile (and mcs if it exists)
|
||||
local(f"cp {bit_path} {tar_staging_path}")
|
||||
if self.build_config.PLATFORM != "xilinx_vcu118":
|
||||
local(f"cp {mcs_path} {tar_staging_path}")
|
||||
if self.build_config.PLATFORM == "xilinx_vcu118":
|
||||
local(f"cp {mcs_secondary_path} {tar_staging_path}")
|
||||
|
||||
# store metadata string
|
||||
local(f"""echo '{self.get_metadata_string()}' >> {tar_staging_path}/metadata""")
|
||||
|
|
@ -848,4 +850,3 @@ class RHSResearchNitefuryIIBitBuilder(XilinxAlveoBitBuilder):
|
|||
rootLogger.debug(rsync_cap.stderr)
|
||||
|
||||
return f"{dest_alveo_dir}/{fpga_build_postfix}"
|
||||
|
||||
|
|
|
|||
|
|
@ -11,12 +11,12 @@
|
|||
|
||||
# DOCREF START: Example HWDB Entry
|
||||
firesim_boom_singlecore_nic_l2_llc4mb_ddr3:
|
||||
agfi: agfi-00e99bd64c0643ac9
|
||||
agfi: agfi-03332c26b0bfef9cf
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
# DOCREF END: Example HWDB Entry
|
||||
firesim_boom_singlecore_no_nic_l2_llc4mb_ddr3:
|
||||
agfi: agfi-0d475d004a5929ce1
|
||||
agfi: agfi-0b01cb001eb3db84b
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
firesim_gemmini_printf_rocket_singlecore_no_nic:
|
||||
|
|
@ -28,11 +28,11 @@ firesim_gemmini_rocket_singlecore_no_nic:
|
|||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
firesim_rocket_quadcore_nic_l2_llc4mb_ddr3:
|
||||
agfi: agfi-03c40fa49ed5c84e8
|
||||
agfi: agfi-0d37db88b8d6a9ea9
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
firesim_rocket_quadcore_no_nic_l2_llc4mb_ddr3:
|
||||
agfi: agfi-0e55df16a9ca937aa
|
||||
agfi: agfi-05ad3a0d05b659fe8
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
firesim_rocket_singlecore_no_nic_l2_lbp:
|
||||
|
|
@ -52,11 +52,11 @@ firesim_rocket_singlecore_sha3_no_nic_l2_llc4mb_ddr3_printf:
|
|||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
firesim_supernode_rocket_singlecore_nic_l2_lbp:
|
||||
agfi: agfi-049822fd73bc2fca1
|
||||
agfi: agfi-0541dd890b2b59bd5
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
vitis_firesim_rocket_singlecore_no_nic:
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/72d12f12eb24fa99e5943723990c1d44df054006/vitis/vitis_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/f17bff0afb96d278c3cd199a72d9317b1bebbb2a/vitis/vitis_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
vitis_firesim_gemmini_rocket_singlecore_no_nic:
|
||||
|
|
@ -64,26 +64,26 @@ vitis_firesim_gemmini_rocket_singlecore_no_nic:
|
|||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
alveo_u250_firesim_rocket_singlecore_no_nic:
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/1dc6be48bfe043bbc47e24660c1ef5076a22b7e4/xilinx_alveo_u250/alveo_u250_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/9543b082437e3ec2c3ecc863da4e06a19597e5e6/xilinx_alveo_u250/alveo_u250_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
alveo_u250_firesim_gemmini_rocket_singlecore_no_nic:
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/9de6c6cd854ff613114b04a2c67d7558e55d456c/xilinx_alveo_u250/alveo_u250_firesim_gemmini_rocket_singlecore_no_nic.tar.gz
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/933a8726645fd7241f019463df86f3d117a7d714/xilinx_alveo_u250/alveo_u250_firesim_gemmini_rocket_singlecore_no_nic.tar.gz
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
alveo_u200_firesim_rocket_singlecore_no_nic:
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/0abb07d46eced6b54e07026533f85bdc73f5a15e/xilinx_alveo_u200/alveo_u200_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/0d91a839113ab048abfed7e79fe2b0d1097f2807/xilinx_alveo_u200/alveo_u200_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
alveo_u280_firesim_rocket_singlecore_no_nic:
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/f445dd689c74d9e9c8e5fdba19e299488f9446ce/xilinx_alveo_u280/alveo_u280_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/a8b9ffaeb4d243292c04eb13857a7daa8ac6d897/xilinx_alveo_u280/alveo_u280_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic:
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/df66683984628552f25acba52e5247ed78321994/xilinx_vcu118/xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic.tar.gz
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/48934d5a7b6b5869b446378656cf61824961471e/xilinx_vcu118/xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic.tar.gz
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
nitefury_firesim_rocket_singlecore_no_nic:
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/b06e34569c2e4b350f8adeb96168244f2d43422b/rhsresearch_nitefury_ii/nitefury_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/f228aa51f95c3a7022444516051fd2fe346cc48d/rhsresearch_nitefury_ii/nitefury_firesim_rocket_singlecore_no_nic.tar.gz
|
||||
deploy_quintuplet_override: null
|
||||
custom_runtime_config: null
|
||||
|
|
@ -3,7 +3,7 @@ run_farm:
|
|||
recipe_arg_overrides:
|
||||
run_farm_tag: helloworldlocalhost
|
||||
default_platform: VitisInstanceDeployManager
|
||||
default_simulation_dir: /scratch/buildbot
|
||||
default_simulation_dir: /scratch/buildbot/RUN_DIR
|
||||
run_farm_hosts_to_use:
|
||||
- localhost: four_metasims_spec
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ run_farm:
|
|||
recipe_arg_overrides:
|
||||
run_farm_tag: helloworldlocalhost
|
||||
default_platform: EC2InstanceDeployManager
|
||||
default_simulation_dir: /home/centos
|
||||
default_simulation_dir: /home/centos/RUN_DIR
|
||||
run_farm_hosts_to_use:
|
||||
- localhost: four_metasims_spec
|
||||
|
||||
|
|
|
|||
|
|
@ -2,14 +2,9 @@ run_farm:
|
|||
base_recipe: run-farm-recipes/externally_provisioned.yaml
|
||||
recipe_arg_overrides:
|
||||
default_platform: VitisInstanceDeployManager
|
||||
default_simulation_dir: /scratch/buildbot
|
||||
default_simulation_dir: /scratch/buildbot/RUN_DIR
|
||||
run_farm_hosts_to_use:
|
||||
- localhost: four_fpgas_spec
|
||||
run_farm_host_specs:
|
||||
- four_fpgas_spec:
|
||||
num_fpgas: 4
|
||||
num_metasims: 0
|
||||
use_for_switch_only: false
|
||||
- harp: one_fpga_spec
|
||||
|
||||
metasimulation:
|
||||
metasimulation_enabled: false
|
||||
|
|
|
|||
|
|
@ -413,7 +413,7 @@ Specifies the host FPGA frequency for a bitstream build.
|
|||
|
||||
Specifies a pre-canned set of strategies and directives to pass to the
|
||||
bitstream build. Note, these are implemented differently on different host
|
||||
platforms, but try to optimize for the same things. Strategies supported across both Vitis, Xilinx Alveo U250/U280, and EC2 F1 include:
|
||||
platforms, but try to optimize for the same things. Strategies supported across both Vitis, Xilinx Alveo U200/U250/U280, and EC2 F1 include:
|
||||
|
||||
- ``TIMING``: Optimize for improved fmax.
|
||||
- ``AREA``: Optimize for reduced resource utilization.
|
||||
|
|
@ -748,7 +748,7 @@ simulations across all run farm hosts.
|
|||
For example, this class manages how to flash FPGAs with bitstreams, how to copy back results, and how to check if a simulation is running.
|
||||
By default, deploy platform classes can be found in :gh-file-ref:`deploy/runtools/run_farm_deploy_managers.py`. However, you can specify
|
||||
your own custom run farm classes by adding your python file to the ``PYTHONPATH``.
|
||||
There are default deploy managers / platforms that correspond to AWS EC2 F1 FPGAs, Vitis FPGAs, Xilinx Alveo U250/U280 FPGAs, Xilinx VCU118 FPGAs, and RHS Research Nitefury II FPGAs: ``EC2InstanceDeployManager``, ``VitisInstanceDeployManager``, ``Xilinx{AlveoU250,AlveoU280,VCU118}InstanceDeployManager``, and ``RHSResearchNitefuryIIInstanceDeployManager`` respectively.
|
||||
There are default deploy managers / platforms that correspond to AWS EC2 F1 FPGAs, Vitis FPGAs, Xilinx Alveo U200/U250/U280 FPGAs, Xilinx VCU118 FPGAs, and RHS Research Nitefury II FPGAs: ``EC2InstanceDeployManager``, ``VitisInstanceDeployManager``, ``Xilinx{AlveoU200,AlveoU250,AlveoU280,VCU118}InstanceDeployManager``, and ``RHSResearchNitefuryIIInstanceDeployManager`` respectively.
|
||||
For example, to use the ``EC2InstanceDeployManager`` deploy platform class, you would write ``default_platform: EC2InstanceDeployManager``.
|
||||
|
||||
``default_simulation_dir``
|
||||
|
|
@ -948,6 +948,11 @@ Here is an example of this configuration file:
|
|||
.. literalinclude:: /../deploy/bit-builder-recipes/vitis.yaml
|
||||
:language: yaml
|
||||
|
||||
``xilinx_alveo_u200.yaml`` bit builder recipe
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
This bit builder recipe configures a build farm host to build an Xilinx Alveo U200 bitstream, packaged into a ``bitstream_tar``.
|
||||
|
||||
``xilinx_alveo_u250.yaml`` bit builder recipe
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
|
|
@ -967,4 +972,3 @@ This bit builder recipe configures a build farm host to build an Xilinx VCU118 b
|
|||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
This bit builder recipe configures a build farm host to build an RHS Research Nitefury II bitstream, packaged into a ``bitstream_tar``.
|
||||
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ Then, do platform-specific init steps for the given ``--platform``.
|
|||
|
||||
.. tab:: All other platforms
|
||||
|
||||
This includes platforms such as: ``xilinx_alveo_u250``, ``xilinx_alveo_u280``, ``xilinx_vcu118``, and ``rhsresearch_nitefury_ii``.
|
||||
This includes platforms such as: ``xilinx_alveo_u200``, ``xilinx_alveo_u250``, ``xilinx_alveo_u280``, ``xilinx_vcu118``, and ``rhsresearch_nitefury_ii``.
|
||||
|
||||
* Setup the ``config_runtime.yaml`` and ``config_build.yaml`` files with externally provisioned run/build farm arguments.
|
||||
|
||||
|
|
@ -426,4 +426,3 @@ used to run simulations for each FPGA attached to the machine.
|
|||
If you ever change the physical layout of a Run Farm Machine in your Run Farm
|
||||
(e.g., which PCIe slot the FPGAs are attached to), you will need to re-run this
|
||||
command.
|
||||
|
||||
|
|
|
|||
|
|
@ -87,6 +87,10 @@ FireSim supports many types of FPGAs and FPGA platforms! Click one of the follow
|
|||
|
||||
* Status: ✅ All FireSim Features Supported.
|
||||
|
||||
* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U200-FPGAs`
|
||||
|
||||
* Status: ✅ All FireSim Features Supported.
|
||||
|
||||
* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs`
|
||||
|
||||
* Status: ✅ All FireSim Features Supported.
|
||||
|
|
@ -106,4 +110,3 @@ FireSim supports many types of FPGAs and FPGA platforms! Click one of the follow
|
|||
* :doc:`Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Vitis-FPGAs`
|
||||
|
||||
* Status: ⚠️ DMA-based Bridges Not Supported. The Vitis-based U250 flow is **not recommended** unless you have specific constraints that require using Vitis. Notably, the Vitis-based flow does not support DMA-based FireSim bridges (e.g., TracerV, Synthesizable Printfs, etc.), while the XDMA-based flows support all FireSim features, as shown above. If you're unsure, use the XDMA-based U250 flow instead: :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs`.
|
||||
|
||||
|
|
|
|||
|
|
@ -126,6 +126,7 @@ output format to ``json``. You will need to generate an AWS access key in the "S
|
|||
Again on the ``t2.nano`` instance, do the following:
|
||||
|
||||
.. code-block:: bash
|
||||
:substitutions:
|
||||
|
||||
sudo yum install -y python3-pip
|
||||
sudo python3 -m pip install boto3
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
.. |fpga_name| replace:: Xilinx Alveo U200
|
||||
.. |hwdb_entry_name| replace:: ``alveo_u200_firesim_rocket_singlecore_no_nic``
|
||||
.. |hwdb_entry_name_non_code| replace:: alveo_u200_firesim_rocket_singlecore_no_nic
|
||||
.. |builder_name| replace:: Xilinx Vivado
|
||||
.. |bit_builder_path| replace:: ``bit-builder-recipes/xilinx_alveo_u200.yaml``
|
||||
.. |vivado_with_version| replace:: Vivado 2021.1
|
||||
.. |vivado_version_number_only| replace:: 2021.1
|
||||
.. |vivado_default_install_path| replace:: ``/tools/Xilinx/Vivado/2021.1``
|
||||
.. |board_package_install| replace:: Download the ``au200`` board support package directory from https://github.com/Xilinx/open-nic-shell/tree/main/board_files/Xilinx and place the directory in ``/tools/Xilinx/Vivado/2021.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/``.
|
||||
|
||||
Building Your Own Hardware Designs
|
||||
===================================================================
|
||||
|
||||
This section will guide you through building a |fpga_name| FPGA bitstream to run FireSim simulations.
|
||||
|
||||
.. include:: Xilinx-XDMA-Build-Farm-Setup-Template.rst
|
||||
|
||||
.. include:: Xilinx-All-Bitstream-Template.rst
|
||||
|
|
@ -3,9 +3,9 @@
|
|||
.. |hwdb_entry_name_non_code| replace:: xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic
|
||||
.. |builder_name| replace:: Xilinx Vivado
|
||||
.. |bit_builder_path| replace:: ``bit-builder-recipes/xilinx_vcu118.yaml``
|
||||
.. |vivado_with_version| replace:: Vivado 2019.1
|
||||
.. |vivado_version_number_only| replace:: 2019.1
|
||||
.. |vivado_default_install_path| replace:: ``/tools/Xilinx/Vivado/2019.1``
|
||||
.. |vivado_with_version| replace:: Vivado 2023.1
|
||||
.. |vivado_version_number_only| replace:: 2023.1
|
||||
.. |vivado_default_install_path| replace:: ``/tools/Xilinx/Vivado/2023.1``
|
||||
.. |board_package_install| replace:: No special board support package is required for the VCU118. Move on to the next step.
|
||||
|
||||
Building Your Own Hardware Designs
|
||||
|
|
|
|||
|
|
@ -11,6 +11,10 @@
|
|||
.. |fpga_spi_part_number| replace:: ``s25fl256xxxxxx0-spi-x1_x2_x4``
|
||||
.. |fpga_attach_prereq| replace:: into either an open M.2. slot on your machine or into an M.2. to Thunderbolt enclosure (then attach the enclosure to your system via a Thunderbolt cable). We have successfully used this enclosure: https://www.amazon.com/ORICO-Enclosure-Compatible-Thunderbolt-Type-C-M2V01/dp/B08R9DMFFT. Before permanently installing your Nitefury into your M.2. slot or enclosure, ensure that you have attached the ribbon cable that will be used for JTAG to the underside of the board (see step 4 below).
|
||||
.. |jtag_help| replace:: JTAG. For the Nitefury, this requires attaching the 14-pin JTAG adapter included with the board to the board using the included ribbon cable, then attaching a USB to JTAG adapter such as the Digilent HS2: https://digilent.com/shop/jtag-hs2-programming-cable/.
|
||||
.. |extra_mcs| replace:: file from step 7.
|
||||
.. |mcs_info| replace:: Inside, you will find three files; the one we are currently interested in will be called ``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the next step.
|
||||
.. |dip_switch_extra| replace:: power).
|
||||
.. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. For the Nitefury to work, we will need to make one modification to the driver. Find the line containing ``#define XDMA_ENGINE_XFER_MAX_DESC``. Change the value on this line from ``0x800`` to ``16``. Then, build and install the driver:
|
||||
.. |jtag_cable_reminder| replace:: Remember to keep the USB cable for JTAG connected at all times when running FireSim simulations (it is used to program the FPGA).
|
||||
|
||||
.. include:: Xilinx-XDMA-Template.rst
|
||||
|
|
|
|||
|
|
@ -0,0 +1,20 @@
|
|||
.. |fpga_name| replace:: Xilinx Alveo U200
|
||||
.. _fpga_name: https://www.xilinx.com/products/boards-and-kits/alveo/u200.html
|
||||
.. |fpga_power_info| replace:: For the U200, this is usually PCIe power coming directly from the system's PSU.
|
||||
.. |hwdb_entry_name| replace:: ``alveo_u200_firesim_rocket_singlecore_no_nic``
|
||||
.. |platform_name| replace:: xilinx_alveo_u200
|
||||
.. |board_name| replace:: au200
|
||||
.. |tool_type| replace:: Xilinx Vivado
|
||||
.. |tool_type_lab| replace:: Xilinx Vivado Lab
|
||||
.. |example_var| replace:: ``XILINX_VIVADO``
|
||||
.. |deploy_manager_code| replace:: ``XilinxAlveoU200InstanceDeployManager``
|
||||
.. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4``
|
||||
.. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine.
|
||||
.. |jtag_help| replace:: JTAG.
|
||||
.. |extra_mcs| replace:: file from step 7.
|
||||
.. |mcs_info| replace:: Inside, you will find three files; the one we are currently interested in will be called ``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the next step.
|
||||
.. |dip_switch_extra| replace:: power).
|
||||
.. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. Now, let's build and install it:
|
||||
.. |jtag_cable_reminder| replace:: Remember to keep the USB cable for JTAG connected at all times when running FireSim simulations (it is used to program the FPGA).
|
||||
|
||||
.. include:: Xilinx-XDMA-Template.rst
|
||||
|
|
@ -11,6 +11,10 @@
|
|||
.. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4``
|
||||
.. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine.
|
||||
.. |jtag_help| replace:: JTAG.
|
||||
.. |extra_mcs| replace:: file from step 7.
|
||||
.. |mcs_info| replace:: Inside, you will find three files; the one we are currently interested in will be called ``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the next step.
|
||||
.. |dip_switch_extra| replace:: power).
|
||||
.. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. Now, let's build and install it:
|
||||
.. |jtag_cable_reminder| replace:: Remember to keep the USB cable for JTAG connected at all times when running FireSim simulations (it is used to program the FPGA).
|
||||
|
||||
.. include:: Xilinx-XDMA-Template.rst
|
||||
|
|
|
|||
|
|
@ -11,6 +11,10 @@
|
|||
.. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4``
|
||||
.. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine.
|
||||
.. |jtag_help| replace:: JTAG.
|
||||
.. |extra_mcs| replace:: file from step 7.
|
||||
.. |mcs_info| replace:: Inside, you will find three files; the one we are currently interested in will be called ``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the next step.
|
||||
.. |dip_switch_extra| replace:: power).
|
||||
.. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. Now, let's build and install it:
|
||||
.. |jtag_cable_reminder| replace:: Remember to keep the USB cable for JTAG connected at all times when running FireSim simulations (it is used to program the FPGA).
|
||||
|
||||
.. include:: Xilinx-XDMA-Template.rst
|
||||
|
|
|
|||
|
|
@ -8,9 +8,13 @@
|
|||
.. |tool_type_lab| replace:: Xilinx Vivado Lab
|
||||
.. |example_var| replace:: ``XILINX_VIVADO``
|
||||
.. |deploy_manager_code| replace:: ``XilinxVCU118InstanceDeployManager``
|
||||
.. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4``
|
||||
.. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine. Also, ensure that the SW16 switches on the FPGA are set to ``0101`` to enable QSPI flashing over JTAG (i.e., ``position 1 = 0``, ``position 2 = 1``, ``position 3 = 0``, and ``position 4 = 1``. Having the switch set to the side of the position label indicates 0.)
|
||||
.. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4_x8``
|
||||
.. |mcs_info| replace:: Inside, you will find four files; the ones we are currently interested in will be called ``firesim.mcs`` and ``firesim_secondary.mcs``. Note the full path of the ``firesim.mcs`` and ``firesim_secondary.mcs`` files for the next step.
|
||||
.. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine. Also, ensure that the SW16 switches on the board are set to ``0101`` to enable QSPI flashing over JTAG (i.e., ``position 1 = 0``, ``position 2 = 1``, ``position 3 = 0``, and ``position 4 = 1``. Having the switch set to the side of the position label indicates 0.)
|
||||
.. |jtag_help| replace:: JTAG.
|
||||
.. |extra_mcs| replace:: file from step 7 and for Configuration file 2, choose the ``firesim_secondary.mcs`` file from step 7.
|
||||
.. |dip_switch_extra| replace:: power). Then, set the SW16 switches on the board to ``0001`` to set the board to automatically program the FPGA from the QSPI at boot (i.e., ``position 1 = 0``, ``position 2 = 0``, ``position 3 = 0``, and ``position 4 = 1``. Having the switch set to the side of the position label indicates 0.)
|
||||
.. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. Now, let's build and install it:
|
||||
.. |jtag_cable_reminder| replace:: If necessary, you can remove the USB cable for JTAG (the FPGA is programmed through PCIe for FireSim simulations on the Xilinx VCU118). However, we still recommend leaving the cable attached, since it will allow you to re-flash the SPI in case there are issues.
|
||||
|
||||
.. include:: Xilinx-XDMA-Template.rst
|
||||
|
|
|
|||
|
|
@ -187,25 +187,24 @@ Now, let's attach your |fpga_name|_ FPGA(s) to your Run Farm Machines:
|
|||
|
||||
6. Obtain an existing bitstream tar file for your FPGA by opening the ``bitstream_tar`` URL listed
|
||||
under |hwdb_entry_name| in the following file: :gh-file-ref:`deploy/sample-backup-configs/sample_config_hwdb.yaml`.
|
||||
7. Extract the ``.tar.gz`` file to a known location. Inside, you will find
|
||||
three files; the one we are currently interested in will be called
|
||||
``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the
|
||||
next step.
|
||||
7. Extract the ``.tar.gz`` file to a known location. |mcs_info|
|
||||
|
||||
8. Open Vivado Lab and click "Open Hardware Manager". Then click "Open Target" and "Auto connect".
|
||||
|
||||
9. Right-click on your FPGA and click "Add Configuration Memory Device". For a |fpga_name|_, choose |fpga_spi_part_number|
|
||||
as the Configuration Memory Part. Click "OK" when prompted to program the configuration memory device.
|
||||
|
||||
10. For Configuration file, choose the ``firesim.mcs`` file from step 7.
|
||||
10. For Configuration file, choose the ``firesim.mcs`` |extra_mcs|
|
||||
|
||||
11. Uncheck "Verify" and click OK.
|
||||
|
||||
12. When programming the configuration memory device is completed, power off your machine fully (i.e., the FPGA should completely lose power).
|
||||
12. Right-click on your FPGA and click "Boot from Configuration Memory Device".
|
||||
|
||||
13. Cold-boot the machine. A cold boot is required for the FPGA to be successfully re-programmed from its flash.
|
||||
13. When programming the configuration memory device is completed, power off your machine fully (i.e., the FPGA should completely lose |dip_switch_extra|)
|
||||
|
||||
14. Once the machine has booted, run the following to ensure that your FPGA is set up properly:
|
||||
14. Cold-boot the machine. A cold boot is required for the FPGA to be successfully re-programmed from its flash.
|
||||
|
||||
15. Once the machine has booted, run the following to ensure that your FPGA is set up properly:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
|
|
@ -215,6 +214,8 @@ If successful, this should show an entry with Xilinx as the manufacturer and
|
|||
two memory regions. There should be one entry
|
||||
for each FPGA you've added to the Run Farm Machine.
|
||||
|
||||
.. note:: |jtag_cable_reminder|
|
||||
|
||||
|
||||
6. Install sshd
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
|
@ -358,4 +359,3 @@ each Run Farm machine, replacing ``RUN_FARM_IP`` with a different Run Farm Machi
|
|||
IP address.
|
||||
|
||||
Congratulations! We've now set up your machine/cluster to run simulations. Click Next to continue with the guide.
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,11 @@
|
|||
.. |fpga_name| replace:: Xilinx Alveo U200
|
||||
.. _fpga_name: https://www.xilinx.com/products/boards-and-kits/alveo/u200.html
|
||||
.. |hwdb_entry_name| replace:: ``alveo_u200_firesim_rocket_singlecore_no_nic``
|
||||
.. |platform_name| replace:: xilinx_alveo_u200
|
||||
.. |board_name| replace:: au200
|
||||
.. |tool_type| replace:: Xilinx Vivado
|
||||
.. |tool_type_lab| replace:: Xilinx Vivado Lab
|
||||
.. |example_var| replace:: ``XILINX_VIVADO``
|
||||
.. |deploy_manager_code| replace:: ``XilinxAlveoU200InstanceDeployManager``
|
||||
|
||||
.. include:: Xilinx-XDMA-Template.rst
|
||||
|
|
@ -9,7 +9,7 @@ run_farm:
|
|||
default_platform: VitisInstanceDeployManager
|
||||
|
||||
# REQUIRED: default directory where simulations are run out of on the run farm hosts
|
||||
default_simulation_dir: /vm/home/buildbot/FIRESIM_RUNS_DIR
|
||||
default_simulation_dir: /home/buildbot/FIRESIM_RUNS_DIR
|
||||
|
||||
# REQUIRED: List of unique hostnames/IP addresses, each with their
|
||||
# corresponding specification that describes the properties of the host.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
.. |fpga_type| replace:: Xilinx Alveo U200
|
||||
.. |deploy_manager| replace:: XilinxAlveoU200InstanceDeployManager
|
||||
.. |deploy_manager_code| replace:: ``XilinxAlveoU200InstanceDeployManager``
|
||||
.. |runner| replace:: Xilinx Vivado
|
||||
.. |hwdb_entry_name| replace:: alveo_u200_firesim_rocket_singlecore_no_nic
|
||||
|
||||
.. include:: Running-Single-Node-Simulation-Template.rst
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
.. |fpga_name| replace:: Xilinx Alveo U200 XDMA-based
|
||||
.. |fpga_name_short| replace:: Xilinx Alveo U200
|
||||
.. _fpga_name_short: https://www.xilinx.com/products/boards-and-kits/alveo/u200.html
|
||||
.. |flow_name| replace:: XDMA-based
|
||||
.. |build_type| replace:: Xilinx Vivado
|
||||
|
||||
.. _u200-standard-flow:
|
||||
|
||||
.. include:: Intro-Template.rst
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 3
|
||||
|
||||
Initial-Setup/Xilinx-Alveo-U200
|
||||
Repo-Setup/Xilinx-Alveo-U200
|
||||
Running-Simulations/Running-Single-Node-Simulation-Xilinx-Alveo-U200
|
||||
Building-a-FireSim-Bitstream/Xilinx-Alveo-U200
|
||||
|
|
@ -10,6 +10,7 @@ New to FireSim? Jump to the :doc:`/FireSim-Basics` page for more info.
|
|||
|
||||
FireSim-Basics
|
||||
Getting-Started-Guides/AWS-EC2-F1-Getting-Started/index
|
||||
Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U200-FPGAs
|
||||
Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs
|
||||
Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U280-FPGAs
|
||||
Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-VCU118-FPGAs
|
||||
|
|
|
|||
|
|
@ -0,0 +1,386 @@
|
|||
################################################################
|
||||
# This is a generated script based on design: design_1
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2022.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
# The design that will be created by this Tcl script contains the following
|
||||
# module references:
|
||||
# axi_tieoff_master, firesim_wrapper
|
||||
|
||||
# Please add the sources of those modules before sourcing this Tcl script.
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
variable design_name
|
||||
set design_name design_1
|
||||
|
||||
# If you do not already have an existing IP Integrator design open,
|
||||
# you can create a design using the following command:
|
||||
# create_bd_design $design_name
|
||||
|
||||
# Creating design if needed
|
||||
set errMsg ""
|
||||
set nRet 0
|
||||
|
||||
set cur_design [current_bd_design -quiet]
|
||||
set list_cells [get_bd_cells -quiet]
|
||||
|
||||
if { ${design_name} eq "" } {
|
||||
# USE CASES:
|
||||
# 1) Design_name not set
|
||||
|
||||
set errMsg "Please set the variable <design_name> to a non-empty value."
|
||||
set nRet 1
|
||||
|
||||
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
||||
# USE CASES:
|
||||
# 2): Current design opened AND is empty AND names same.
|
||||
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
# 5) Current design opened AND has components AND same names.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 1
|
||||
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
||||
# USE CASES:
|
||||
# 6) Current opened design, has components, but diff names, design_name exists in project.
|
||||
# 7) No opened design, design_name exists in project.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 2
|
||||
|
||||
} else {
|
||||
# USE CASES:
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
set bCheckIPsPassed 1
|
||||
##################################################################
|
||||
# CHECK IPs
|
||||
##################################################################
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
xilinx.com:ip:axi_clock_converter:2.1\
|
||||
xilinx.com:ip:axi_dwidth_converter:2.1\
|
||||
xilinx.com:ip:clk_wiz:6.0\
|
||||
xilinx.com:ip:ddr4:2.2\
|
||||
xilinx.com:ip:proc_sys_reset:5.0\
|
||||
xilinx.com:ip:util_vector_logic:2.0\
|
||||
xilinx.com:ip:util_ds_buf:2.2\
|
||||
xilinx.com:ip:xdma:4.1\
|
||||
xilinx.com:ip:xlconstant:1.1\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
if { $ip_obj eq "" } {
|
||||
lappend list_ips_missing $ip_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# CHECK Modules
|
||||
##################################################################
|
||||
set bCheckModules 1
|
||||
if { $bCheckModules == 1 } {
|
||||
set list_check_mods "\
|
||||
axi_tieoff_master\
|
||||
firesim_wrapper\
|
||||
"
|
||||
|
||||
set list_mods_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
|
||||
foreach mod_vlnv $list_check_mods {
|
||||
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
||||
lappend list_mods_missing $mod_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_mods_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell firesim_freq } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set ddr4_sdram_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c0 ]
|
||||
|
||||
set default_300mhz_clk0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_300mhz_clk0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {300000000} \
|
||||
] $default_300mhz_clk0
|
||||
|
||||
set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ]
|
||||
|
||||
set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {100000000} \
|
||||
] $pcie_refclk
|
||||
|
||||
|
||||
# Create ports
|
||||
set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $pcie_perstn
|
||||
set resetn [ create_bd_port -dir I -type rst resetn ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $resetn
|
||||
|
||||
# Create instance: axi_clock_converter_0, and set properties
|
||||
set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
|
||||
|
||||
# Create instance: axi_clock_converter_1, and set properties
|
||||
set axi_clock_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_1 ]
|
||||
|
||||
# Create instance: axi_dwidth_converter_0, and set properties
|
||||
set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.MI_DATA_WIDTH {512} \
|
||||
CONFIG.SI_DATA_WIDTH {64} \
|
||||
CONFIG.SI_ID_WIDTH {16} \
|
||||
] $axi_dwidth_converter_0
|
||||
|
||||
|
||||
# Create instance: axi_tieoff_master_0, and set properties
|
||||
set block_name axi_tieoff_master
|
||||
set block_cell_name axi_tieoff_master_0
|
||||
if { [catch {set axi_tieoff_master_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $axi_tieoff_master_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: clk_wiz_0, and set properties
|
||||
set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ $firesim_freq \
|
||||
CONFIG.USE_LOCKED {false} \
|
||||
] $clk_wiz_0
|
||||
|
||||
|
||||
# Create instance: ddr4_0, and set properties
|
||||
set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_AxiAddressWidth {34} \
|
||||
CONFIG.C0.DDR4_EN_PARITY {true} \
|
||||
CONFIG.C0.DDR4_MCS_ECC {false} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \
|
||||
CONFIG.C0_CLOCK_BOARD_INTERFACE {default_300mhz_clk0} \
|
||||
CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0} \
|
||||
CONFIG.Debug_Signal {Disable} \
|
||||
CONFIG.RESET_BOARD_INTERFACE {resetn} \
|
||||
] $ddr4_0
|
||||
|
||||
|
||||
# Create instance: firesim_wrapper_0, and set properties
|
||||
set block_name firesim_wrapper
|
||||
set block_cell_name firesim_wrapper_0
|
||||
if { [catch {set firesim_wrapper_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $firesim_wrapper_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: proc_sys_reset_0, and set properties
|
||||
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
|
||||
|
||||
# Create instance: proc_sys_reset_1, and set properties
|
||||
set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ]
|
||||
|
||||
# Create instance: resetn_inv_0, and set properties
|
||||
set resetn_inv_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 resetn_inv_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.C_OPERATION {not} \
|
||||
CONFIG.C_SIZE {1} \
|
||||
] $resetn_inv_0
|
||||
|
||||
|
||||
# Create instance: util_ds_buf, and set properties
|
||||
set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk} \
|
||||
CONFIG.USE_BOARD_FLOW {true} \
|
||||
] $util_ds_buf
|
||||
|
||||
|
||||
# Create instance: xdma_0, and set properties
|
||||
set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.PCIE_BOARD_INTERFACE {pci_express_x16} \
|
||||
CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \
|
||||
CONFIG.axilite_master_en {true} \
|
||||
CONFIG.axilite_master_size {32} \
|
||||
CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \
|
||||
CONFIG.xdma_rnum_chnl {4} \
|
||||
CONFIG.xdma_wnum_chnl {4} \
|
||||
] $xdma_0
|
||||
|
||||
|
||||
# Create instance: xlconstant_0, and set properties
|
||||
set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
|
||||
set_property CONFIG.CONST_VAL {0} $xlconstant_0
|
||||
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_DMA]
|
||||
connect_bd_intf_net -intf_net axi_clock_converter_1_M_AXI [get_bd_intf_pins axi_clock_converter_1/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_CTRL]
|
||||
connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_tieoff_master_0_TIEOFF_M_AXI_CTRL_0 [get_bd_intf_pins axi_tieoff_master_0/TIEOFF_M_AXI_CTRL_0] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL]
|
||||
connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram_c0] [get_bd_intf_pins ddr4_0/C0_DDR4]
|
||||
connect_bd_intf_net -intf_net default_300mhz_clk0_1 [get_bd_intf_ports default_300mhz_clk0] [get_bd_intf_pins ddr4_0/C0_SYS_CLK]
|
||||
connect_bd_intf_net -intf_net firesim_wrapper_0_M_AXI_DDR0 [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins firesim_wrapper_0/M_AXI_DDR0]
|
||||
connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D]
|
||||
connect_bd_intf_net -intf_net xdma_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins xdma_0/M_AXI]
|
||||
connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins axi_clock_converter_1/S_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE]
|
||||
connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins xdma_0/pcie_mgt]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_dwidth_converter_0/m_axi_aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins proc_sys_reset_1/slowest_sync_clk]
|
||||
connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins xdma_0/sys_rst_n]
|
||||
connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins firesim_wrapper_0/sys_reset_n] [get_bd_pins proc_sys_reset_0/interconnect_aresetn]
|
||||
connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins resetn_inv_0/Op1]
|
||||
connect_bd_net -net resetn_inv_0_Res [get_bd_pins clk_wiz_0/reset] [get_bd_pins ddr4_0/sys_rst] [get_bd_pins resetn_inv_0/Res]
|
||||
connect_bd_net -net rst_ddr4_0_300M_interconnect_aresetn [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||
connect_bd_net -net sys_clk_30 [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins firesim_wrapper_0/sys_clk_30] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
|
||||
connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk]
|
||||
connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins util_ds_buf/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt]
|
||||
connect_bd_net -net xdma_0_axi_aclk [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins xdma_0/axi_aclk]
|
||||
connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins xdma_0/axi_aresetn]
|
||||
connect_bd_net -net xlconstant_0_dout [get_bd_pins xdma_0/usr_irq_req] [get_bd_pins xlconstant_0/dout]
|
||||
|
||||
# Create address segments
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design "" $desired_host_frequency
|
||||
|
|
@ -0,0 +1 @@
|
|||
../../../xilinx_alveo_u250/cl_firesim/scripts/implementation_2022.1.tcl
|
||||
|
|
@ -1 +1 @@
|
|||
set jobs 12
|
||||
set jobs 8
|
||||
|
|
|
|||
|
|
@ -0,0 +1,386 @@
|
|||
################################################################
|
||||
# This is a generated script based on design: design_1
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2022.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
# The design that will be created by this Tcl script contains the following
|
||||
# module references:
|
||||
# axi_tieoff_master, firesim_wrapper
|
||||
|
||||
# Please add the sources of those modules before sourcing this Tcl script.
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
variable design_name
|
||||
set design_name design_1
|
||||
|
||||
# If you do not already have an existing IP Integrator design open,
|
||||
# you can create a design using the following command:
|
||||
# create_bd_design $design_name
|
||||
|
||||
# Creating design if needed
|
||||
set errMsg ""
|
||||
set nRet 0
|
||||
|
||||
set cur_design [current_bd_design -quiet]
|
||||
set list_cells [get_bd_cells -quiet]
|
||||
|
||||
if { ${design_name} eq "" } {
|
||||
# USE CASES:
|
||||
# 1) Design_name not set
|
||||
|
||||
set errMsg "Please set the variable <design_name> to a non-empty value."
|
||||
set nRet 1
|
||||
|
||||
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
||||
# USE CASES:
|
||||
# 2): Current design opened AND is empty AND names same.
|
||||
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
# 5) Current design opened AND has components AND same names.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 1
|
||||
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
||||
# USE CASES:
|
||||
# 6) Current opened design, has components, but diff names, design_name exists in project.
|
||||
# 7) No opened design, design_name exists in project.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 2
|
||||
|
||||
} else {
|
||||
# USE CASES:
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
set bCheckIPsPassed 1
|
||||
##################################################################
|
||||
# CHECK IPs
|
||||
##################################################################
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
xilinx.com:ip:axi_clock_converter:2.1\
|
||||
xilinx.com:ip:axi_dwidth_converter:2.1\
|
||||
xilinx.com:ip:clk_wiz:6.0\
|
||||
xilinx.com:ip:ddr4:2.2\
|
||||
xilinx.com:ip:proc_sys_reset:5.0\
|
||||
xilinx.com:ip:util_vector_logic:2.0\
|
||||
xilinx.com:ip:util_ds_buf:2.2\
|
||||
xilinx.com:ip:xdma:4.1\
|
||||
xilinx.com:ip:xlconstant:1.1\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
if { $ip_obj eq "" } {
|
||||
lappend list_ips_missing $ip_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# CHECK Modules
|
||||
##################################################################
|
||||
set bCheckModules 1
|
||||
if { $bCheckModules == 1 } {
|
||||
set list_check_mods "\
|
||||
axi_tieoff_master\
|
||||
firesim_wrapper\
|
||||
"
|
||||
|
||||
set list_mods_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
|
||||
foreach mod_vlnv $list_check_mods {
|
||||
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
||||
lappend list_mods_missing $mod_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_mods_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell firesim_freq } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set ddr4_sdram_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c0 ]
|
||||
|
||||
set default_300mhz_clk0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_300mhz_clk0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {300000000} \
|
||||
] $default_300mhz_clk0
|
||||
|
||||
set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ]
|
||||
|
||||
set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {100000000} \
|
||||
] $pcie_refclk
|
||||
|
||||
|
||||
# Create ports
|
||||
set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $pcie_perstn
|
||||
set resetn [ create_bd_port -dir I -type rst resetn ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $resetn
|
||||
|
||||
# Create instance: axi_clock_converter_0, and set properties
|
||||
set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
|
||||
|
||||
# Create instance: axi_clock_converter_1, and set properties
|
||||
set axi_clock_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_1 ]
|
||||
|
||||
# Create instance: axi_dwidth_converter_0, and set properties
|
||||
set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.MI_DATA_WIDTH {512} \
|
||||
CONFIG.SI_DATA_WIDTH {64} \
|
||||
CONFIG.SI_ID_WIDTH {16} \
|
||||
] $axi_dwidth_converter_0
|
||||
|
||||
|
||||
# Create instance: axi_tieoff_master_0, and set properties
|
||||
set block_name axi_tieoff_master
|
||||
set block_cell_name axi_tieoff_master_0
|
||||
if { [catch {set axi_tieoff_master_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $axi_tieoff_master_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: clk_wiz_0, and set properties
|
||||
set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ $firesim_freq \
|
||||
CONFIG.USE_LOCKED {false} \
|
||||
] $clk_wiz_0
|
||||
|
||||
|
||||
# Create instance: ddr4_0, and set properties
|
||||
set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_AxiAddressWidth {34} \
|
||||
CONFIG.C0.DDR4_EN_PARITY {true} \
|
||||
CONFIG.C0.DDR4_MCS_ECC {false} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \
|
||||
CONFIG.C0_CLOCK_BOARD_INTERFACE {default_300mhz_clk0} \
|
||||
CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0} \
|
||||
CONFIG.Debug_Signal {Disable} \
|
||||
CONFIG.RESET_BOARD_INTERFACE {resetn} \
|
||||
] $ddr4_0
|
||||
|
||||
|
||||
# Create instance: firesim_wrapper_0, and set properties
|
||||
set block_name firesim_wrapper
|
||||
set block_cell_name firesim_wrapper_0
|
||||
if { [catch {set firesim_wrapper_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $firesim_wrapper_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: proc_sys_reset_0, and set properties
|
||||
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
|
||||
|
||||
# Create instance: proc_sys_reset_1, and set properties
|
||||
set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ]
|
||||
|
||||
# Create instance: resetn_inv_0, and set properties
|
||||
set resetn_inv_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 resetn_inv_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.C_OPERATION {not} \
|
||||
CONFIG.C_SIZE {1} \
|
||||
] $resetn_inv_0
|
||||
|
||||
|
||||
# Create instance: util_ds_buf, and set properties
|
||||
set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk} \
|
||||
CONFIG.USE_BOARD_FLOW {true} \
|
||||
] $util_ds_buf
|
||||
|
||||
|
||||
# Create instance: xdma_0, and set properties
|
||||
set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.PCIE_BOARD_INTERFACE {pci_express_x16} \
|
||||
CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \
|
||||
CONFIG.axilite_master_en {true} \
|
||||
CONFIG.axilite_master_size {32} \
|
||||
CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \
|
||||
CONFIG.xdma_rnum_chnl {4} \
|
||||
CONFIG.xdma_wnum_chnl {4} \
|
||||
] $xdma_0
|
||||
|
||||
|
||||
# Create instance: xlconstant_0, and set properties
|
||||
set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
|
||||
set_property CONFIG.CONST_VAL {0} $xlconstant_0
|
||||
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_DMA]
|
||||
connect_bd_intf_net -intf_net axi_clock_converter_1_M_AXI [get_bd_intf_pins axi_clock_converter_1/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_CTRL]
|
||||
connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_tieoff_master_0_TIEOFF_M_AXI_CTRL_0 [get_bd_intf_pins axi_tieoff_master_0/TIEOFF_M_AXI_CTRL_0] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL]
|
||||
connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram_c0] [get_bd_intf_pins ddr4_0/C0_DDR4]
|
||||
connect_bd_intf_net -intf_net default_300mhz_clk0_1 [get_bd_intf_ports default_300mhz_clk0] [get_bd_intf_pins ddr4_0/C0_SYS_CLK]
|
||||
connect_bd_intf_net -intf_net firesim_wrapper_0_M_AXI_DDR0 [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins firesim_wrapper_0/M_AXI_DDR0]
|
||||
connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D]
|
||||
connect_bd_intf_net -intf_net xdma_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins xdma_0/M_AXI]
|
||||
connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins axi_clock_converter_1/S_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE]
|
||||
connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins xdma_0/pcie_mgt]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_dwidth_converter_0/m_axi_aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins proc_sys_reset_1/slowest_sync_clk]
|
||||
connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins xdma_0/sys_rst_n]
|
||||
connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins firesim_wrapper_0/sys_reset_n] [get_bd_pins proc_sys_reset_0/interconnect_aresetn]
|
||||
connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins resetn_inv_0/Op1]
|
||||
connect_bd_net -net resetn_inv_0_Res [get_bd_pins clk_wiz_0/reset] [get_bd_pins ddr4_0/sys_rst] [get_bd_pins resetn_inv_0/Res]
|
||||
connect_bd_net -net rst_ddr4_0_300M_interconnect_aresetn [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||
connect_bd_net -net sys_clk_30 [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins firesim_wrapper_0/sys_clk_30] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
|
||||
connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk]
|
||||
connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins util_ds_buf/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt]
|
||||
connect_bd_net -net xdma_0_axi_aclk [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins xdma_0/axi_aclk]
|
||||
connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins xdma_0/axi_aresetn]
|
||||
connect_bd_net -net xlconstant_0_dout [get_bd_pins xdma_0/usr_irq_req] [get_bd_pins xlconstant_0/dout]
|
||||
|
||||
# Create address segments
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design "" $desired_host_frequency
|
||||
|
|
@ -0,0 +1 @@
|
|||
implementation_2022.2.tcl
|
||||
|
|
@ -0,0 +1 @@
|
|||
implementation_idr_2022.2.tcl
|
||||
|
|
@ -1 +1 @@
|
|||
set jobs 12
|
||||
set jobs 8
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
import subprocess
|
||||
import sys
|
||||
import re
|
||||
import time
|
||||
from pathlib import Path
|
||||
|
||||
from typing import Dict, List
|
||||
|
|
@ -102,6 +103,7 @@ def clear_serr_bits(bus_id: str) -> None:
|
|||
run = subprocess.run(['setpci', '-s', bridgeBDF, 'COMMAND=0000:0100'])
|
||||
if run.returncode != 0:
|
||||
sys.exit(f":ERROR: Unable to clear SERR bit for {bridgeBDF}")
|
||||
time.sleep(1)
|
||||
|
||||
# clear fatal error reporting enable bit in the device control register
|
||||
# https://support.xilinx.com/s/question/0D52E00006hpjPHSAY/dell-r720-poweredge-server-reboots-on-fpga-reprogramming?language=en_US
|
||||
|
|
@ -110,6 +112,7 @@ def clear_fatal_error_reporting_bits(bus_id: str) -> None:
|
|||
run = subprocess.run(['setpci', '-s', bridgeBDF, 'CAP_EXP+8.w=0000:0004'])
|
||||
if run.returncode != 0:
|
||||
sys.exit(f":ERROR: Unable to clear error reporting bit for {bridgeBDF}")
|
||||
time.sleep(1)
|
||||
|
||||
def write_to_linux_device_path(path: Path, data: str = '1\n') -> None:
|
||||
try:
|
||||
|
|
@ -117,6 +120,7 @@ def write_to_linux_device_path(path: Path, data: str = '1\n') -> None:
|
|||
open(path, 'w').write(data)
|
||||
except:
|
||||
sys.exit(f":ERROR: Cannot write to {path} value: {data}")
|
||||
time.sleep(1)
|
||||
|
||||
def remove(bus_id: str) -> None:
|
||||
for devicePaths in get_device_paths(bus_id):
|
||||
|
|
@ -138,6 +142,7 @@ def enable_memmapped_transfers(bus_id: str) -> None:
|
|||
run = subprocess.run(['setpci', '-s', deviceBDF, 'COMMAND=0x02'])
|
||||
if run.returncode != 0:
|
||||
sys.exit(f":ERROR: Unable to enable memmapped transfers on {deviceBDF}")
|
||||
time.sleep(1)
|
||||
|
||||
def any_device_exists(bus_id: str) -> bool:
|
||||
return len(get_device_paths(bus_id)) > 0
|
||||
|
|
|
|||
|
|
@ -0,0 +1,387 @@
|
|||
################################################################
|
||||
# This is a generated script based on design: design_1
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2022.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
|
||||
# The design that will be created by this Tcl script contains the following
|
||||
# module references:
|
||||
# axi_tieoff_master, firesim_wrapper
|
||||
|
||||
# Please add the sources of those modules before sourcing this Tcl script.
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
variable design_name
|
||||
set design_name design_1
|
||||
|
||||
# If you do not already have an existing IP Integrator design open,
|
||||
# you can create a design using the following command:
|
||||
# create_bd_design $design_name
|
||||
|
||||
# Creating design if needed
|
||||
set errMsg ""
|
||||
set nRet 0
|
||||
|
||||
set cur_design [current_bd_design -quiet]
|
||||
set list_cells [get_bd_cells -quiet]
|
||||
|
||||
if { ${design_name} eq "" } {
|
||||
# USE CASES:
|
||||
# 1) Design_name not set
|
||||
|
||||
set errMsg "Please set the variable <design_name> to a non-empty value."
|
||||
set nRet 1
|
||||
|
||||
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
||||
# USE CASES:
|
||||
# 2): Current design opened AND is empty AND names same.
|
||||
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
# 5) Current design opened AND has components AND same names.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 1
|
||||
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
||||
# USE CASES:
|
||||
# 6) Current opened design, has components, but diff names, design_name exists in project.
|
||||
# 7) No opened design, design_name exists in project.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 2
|
||||
|
||||
} else {
|
||||
# USE CASES:
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
set bCheckIPsPassed 1
|
||||
##################################################################
|
||||
# CHECK IPs
|
||||
##################################################################
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
xilinx.com:ip:axi_clock_converter:2.1\
|
||||
xilinx.com:ip:axi_dwidth_converter:2.1\
|
||||
xilinx.com:ip:clk_wiz:6.0\
|
||||
xilinx.com:ip:ddr4:2.2\
|
||||
xilinx.com:ip:proc_sys_reset:5.0\
|
||||
xilinx.com:ip:util_vector_logic:2.0\
|
||||
xilinx.com:ip:util_ds_buf:2.2\
|
||||
xilinx.com:ip:xdma:4.1\
|
||||
xilinx.com:ip:xlconstant:1.1\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
if { $ip_obj eq "" } {
|
||||
lappend list_ips_missing $ip_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# CHECK Modules
|
||||
##################################################################
|
||||
set bCheckModules 1
|
||||
if { $bCheckModules == 1 } {
|
||||
set list_check_mods "\
|
||||
axi_tieoff_master\
|
||||
firesim_wrapper\
|
||||
"
|
||||
|
||||
set list_mods_missing ""
|
||||
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
|
||||
foreach mod_vlnv $list_check_mods {
|
||||
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
||||
lappend list_mods_missing $mod_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_mods_missing ne "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell firesim_freq } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set ddr4_sdram_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c0 ]
|
||||
|
||||
set sysclk0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sysclk0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {100000000} \
|
||||
] $sysclk0
|
||||
|
||||
set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ]
|
||||
|
||||
set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {100000000} \
|
||||
] $pcie_refclk
|
||||
|
||||
|
||||
# Create ports
|
||||
set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $pcie_perstn
|
||||
set resetn [ create_bd_port -dir I -type rst resetn ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $resetn
|
||||
|
||||
# Create instance: axi_clock_converter_0, and set properties
|
||||
set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
|
||||
|
||||
# Create instance: axi_clock_converter_1, and set properties
|
||||
set axi_clock_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_1 ]
|
||||
|
||||
# Create instance: axi_dwidth_converter_0, and set properties
|
||||
set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.ACLK_ASYNC {1} \
|
||||
CONFIG.FIFO_MODE {2} \
|
||||
CONFIG.MI_DATA_WIDTH {512} \
|
||||
CONFIG.SI_DATA_WIDTH {64} \
|
||||
CONFIG.SI_ID_WIDTH {16} \
|
||||
] $axi_dwidth_converter_0
|
||||
|
||||
|
||||
# Create instance: axi_tieoff_master_0, and set properties
|
||||
set block_name axi_tieoff_master
|
||||
set block_cell_name axi_tieoff_master_0
|
||||
if { [catch {set axi_tieoff_master_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $axi_tieoff_master_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: clk_wiz_0, and set properties
|
||||
set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ $firesim_freq \
|
||||
CONFIG.USE_LOCKED {false} \
|
||||
] $clk_wiz_0
|
||||
|
||||
|
||||
# Create instance: ddr4_0, and set properties
|
||||
set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_AxiAddressWidth {34} \
|
||||
CONFIG.C0.DDR4_EN_PARITY {true} \
|
||||
CONFIG.C0.DDR4_MCS_ECC {false} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \
|
||||
CONFIG.C0_CLOCK_BOARD_INTERFACE {sysclk0} \
|
||||
CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0} \
|
||||
CONFIG.Debug_Signal {Disable} \
|
||||
CONFIG.RESET_BOARD_INTERFACE {resetn} \
|
||||
] $ddr4_0
|
||||
|
||||
|
||||
# Create instance: firesim_wrapper_0, and set properties
|
||||
set block_name firesim_wrapper
|
||||
set block_cell_name firesim_wrapper_0
|
||||
if { [catch {set firesim_wrapper_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $firesim_wrapper_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: proc_sys_reset_0, and set properties
|
||||
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
|
||||
|
||||
# Create instance: proc_sys_reset_1, and set properties
|
||||
set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ]
|
||||
|
||||
# Create instance: resetn_inv_0, and set properties
|
||||
set resetn_inv_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 resetn_inv_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.C_OPERATION {not} \
|
||||
CONFIG.C_SIZE {1} \
|
||||
] $resetn_inv_0
|
||||
|
||||
|
||||
# Create instance: util_ds_buf, and set properties
|
||||
set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ]
|
||||
set_property -dict [list \
|
||||
CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk} \
|
||||
CONFIG.USE_BOARD_FLOW {true} \
|
||||
] $util_ds_buf
|
||||
|
||||
|
||||
# Create instance: xdma_0, and set properties
|
||||
set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ]
|
||||
set_property -dict [list \
|
||||
CONFIG.PCIE_BOARD_INTERFACE {pci_express_x16} \
|
||||
CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \
|
||||
CONFIG.axilite_master_en {true} \
|
||||
CONFIG.axilite_master_size {32} \
|
||||
CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \
|
||||
CONFIG.xdma_rnum_chnl {4} \
|
||||
CONFIG.xdma_wnum_chnl {4} \
|
||||
] $xdma_0
|
||||
|
||||
|
||||
# Create instance: xlconstant_0, and set properties
|
||||
set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
|
||||
set_property CONFIG.CONST_VAL {0} $xlconstant_0
|
||||
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_DMA]
|
||||
connect_bd_intf_net -intf_net axi_clock_converter_1_M_AXI [get_bd_intf_pins axi_clock_converter_1/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_CTRL]
|
||||
connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_tieoff_master_0_TIEOFF_M_AXI_CTRL_0 [get_bd_intf_pins axi_tieoff_master_0/TIEOFF_M_AXI_CTRL_0] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL]
|
||||
connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram_c0] [get_bd_intf_pins ddr4_0/C0_DDR4]
|
||||
connect_bd_intf_net -intf_net sysclk0_1 [get_bd_intf_ports sysclk0] [get_bd_intf_pins ddr4_0/C0_SYS_CLK]
|
||||
connect_bd_intf_net -intf_net firesim_wrapper_0_M_AXI_DDR0 [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins firesim_wrapper_0/M_AXI_DDR0]
|
||||
connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D]
|
||||
connect_bd_intf_net -intf_net xdma_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins xdma_0/M_AXI]
|
||||
connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins axi_clock_converter_1/S_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE]
|
||||
connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins xdma_0/pcie_mgt]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_dwidth_converter_0/m_axi_aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins proc_sys_reset_1/slowest_sync_clk]
|
||||
connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins xdma_0/sys_rst_n]
|
||||
connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins firesim_wrapper_0/sys_reset_n] [get_bd_pins proc_sys_reset_0/interconnect_aresetn]
|
||||
connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins resetn_inv_0/Op1]
|
||||
connect_bd_net -net resetn_inv_0_Res [get_bd_pins clk_wiz_0/reset] [get_bd_pins ddr4_0/sys_rst] [get_bd_pins resetn_inv_0/Res]
|
||||
connect_bd_net -net rst_ddr4_0_100M_interconnect_aresetn [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||
connect_bd_net -net sys_clk_30 [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins firesim_wrapper_0/sys_clk_30] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
|
||||
connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk]
|
||||
connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins util_ds_buf/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt]
|
||||
connect_bd_net -net xdma_0_axi_aclk [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins xdma_0/axi_aclk]
|
||||
connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins xdma_0/axi_aresetn]
|
||||
connect_bd_net -net xlconstant_0_dout [get_bd_pins xdma_0/usr_irq_req] [get_bd_pins xlconstant_0/dout]
|
||||
|
||||
# Create address segments
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design "" $desired_host_frequency
|
||||
|
|
@ -0,0 +1 @@
|
|||
../../../xilinx_alveo_u250/cl_firesim/scripts/implementation_2022.1.tcl
|
||||
|
|
@ -1 +1 @@
|
|||
set jobs 12
|
||||
set jobs 8
|
||||
|
|
|
|||
|
|
@ -82,3 +82,4 @@ vivado -mode batch -source ../tcl/build.tcl -tclargs $FREQUENCY $STRATEGY $BOARD
|
|||
mkdir -p ../vivado_proj
|
||||
cp example_pblock_partition_partial.bit ../vivado_proj/firesim.bit
|
||||
cp ../../shell/prebuilt/empty_primary.mcs ../vivado_proj/firesim.mcs
|
||||
cp ../../shell/prebuilt/empty_secondary.mcs ../vivado_proj/firesim_secondary.mcs
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Subproject commit 8bf28f59b0ef72fd2bc3bce5844ab766fc6c1ddb
|
||||
Subproject commit 4e62dfa8016402c93f03dd2e0e54270f1c85cfeb
|
||||
|
|
@ -6,4 +6,4 @@ if [ ! -d "$REQS_DIR" ]; then
|
|||
echo "$REQS_DIR does not exist, make sure you're calling this script from firesim/"
|
||||
exit 1
|
||||
fi
|
||||
conda-lock -f "$REQS_DIR/firesim.yaml" -f "$REQS_DIR/ci-shared.yaml" -p linux-64 --lockfile "$REQS_DIR/conda-reqs.conda-lock.yml"
|
||||
conda-lock --conda $(which conda) -f "$REQS_DIR/firesim.yaml" -f "$REQS_DIR/ci-shared.yaml" -p linux-64 --lockfile "$REQS_DIR/conda-reqs.conda-lock.yml"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
import Tests._
|
||||
|
||||
val chiselVersion = "3.5.6"
|
||||
val chiselVersion = "3.6.0"
|
||||
|
||||
// keep chisel/firrtl specific class files, rename other conflicts
|
||||
val chiselFirrtlMergeStrategy = CustomMergeStrategy.rename { dep =>
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
// See LICENSE for license details.
|
||||
|
||||
package midas.unittest
|
||||
|
||||
import chisel3._
|
||||
|
|
@ -34,4 +35,3 @@ class Midas2QoRTargets extends Config((site, here, up) => {
|
|||
)
|
||||
}
|
||||
})
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
|
||||
// See LICENSE for license details.
|
||||
|
||||
package midas.core
|
||||
|
|
|
|||
|
|
@ -99,7 +99,6 @@ object SimUtils {
|
|||
// Simple wrapper for nested bundles.
|
||||
private class BundleRecord(elms: Seq[(String, Data)]) extends Record {
|
||||
override val elements = ListMap((elms.map { case (name, data) => name -> data.cloneType }):_*)
|
||||
override def cloneType: this.type = new BundleRecord(elms).asInstanceOf[this.type]
|
||||
override def toString: String = s"{${elements.map({case (name, data) => s"${name}: ${data}"}).mkString(", ")}}"
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,6 @@
|
|||
package midas
|
||||
package core
|
||||
|
||||
|
||||
import midas.widgets.BridgeIOAnnotation
|
||||
import midas.passes.fame
|
||||
import midas.passes.fame.{FAMEChannelConnectionAnnotation, DecoupledForwardChannel, FAMEChannelFanoutAnnotation}
|
||||
|
|
@ -192,7 +191,6 @@ abstract class ChannelizedWrapperIO(val config: SimWrapperConfig)
|
|||
|
||||
class ClockRecord(numClocks: Int) extends Record {
|
||||
override val elements = ListMap(Seq.tabulate(numClocks)(i => s"_$i" -> Clock()):_*)
|
||||
override def cloneType = new ClockRecord(numClocks).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
class TargetBoxIO(config: SimWrapperConfig) extends ChannelizedWrapperIO(config) {
|
||||
|
|
@ -212,7 +210,6 @@ class TargetBoxIO(config: SimWrapperConfig) extends ChannelizedWrapperIO(config)
|
|||
override val elements = ListMap((Seq(clockElement) ++ wireElements ++ rvElements):_*) ++
|
||||
// Untokenized ports
|
||||
ListMap("hostClock" -> hostClock, "hostReset" -> hostReset)
|
||||
override def cloneType: this.type = new TargetBoxIO(config).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
class TargetBox(config: SimWrapperConfig) extends BlackBox {
|
||||
|
|
@ -229,7 +226,6 @@ class SimWrapperChannels(config: SimWrapperConfig) extends ChannelizedWrapperIO(
|
|||
}).get
|
||||
|
||||
override val elements = ListMap((Seq(clockElement) ++ wireElements ++ rvElements):_*)
|
||||
override def cloneType: this.type = new SimWrapperChannels(config).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ package midas
|
|||
package models
|
||||
|
||||
import org.chipsalliance.cde.config.Parameters
|
||||
import freechips.rocketchip.util.GenericParameterizedBundle
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
|
|
@ -345,7 +344,7 @@ class FirstReadyFCFSEntry(key: DRAMBaseConfig)(implicit p: Parameters) extends M
|
|||
// timing and resource constraints are met. The controller must also ensure CAS
|
||||
// commands use the open ROW.
|
||||
|
||||
class BankStateTrackerO(key: DramOrganizationParams) extends GenericParameterizedBundle(key)
|
||||
class BankStateTrackerO(val key: DramOrganizationParams) extends Bundle
|
||||
with CommandLegalBools {
|
||||
|
||||
import DRAMMasEnums._
|
||||
|
|
@ -355,7 +354,7 @@ class BankStateTrackerO(key: DramOrganizationParams) extends GenericParameterize
|
|||
def isRowHit(ref: MASEntry): Bool = ref.rowAddr === openRow && state === bank_active
|
||||
}
|
||||
|
||||
class BankStateTrackerIO(val key: DramOrganizationParams) extends GenericParameterizedBundle(key)
|
||||
class BankStateTrackerIO(val key: DramOrganizationParams) extends Bundle
|
||||
with HasLegalityUpdateIO {
|
||||
val out = new BankStateTrackerO(key)
|
||||
val cmdUsesThisBank = Input(Bool())
|
||||
|
|
@ -443,7 +442,7 @@ class BankStateTracker(key: DramOrganizationParams) extends Module with HasDRAMM
|
|||
// timing and resource constraints are met. The controller must also ensure CAS
|
||||
// commands use the open ROW.
|
||||
|
||||
class RankStateTrackerO(key: DramOrganizationParams) extends GenericParameterizedBundle(key)
|
||||
class RankStateTrackerO(val key: DramOrganizationParams) extends Bundle
|
||||
with CommandLegalBools {
|
||||
import DRAMMasEnums._
|
||||
val canREF = Output(Bool())
|
||||
|
|
@ -452,7 +451,7 @@ class RankStateTrackerO(key: DramOrganizationParams) extends GenericParameterize
|
|||
val banks = Vec(key.maxBanks, Output(new BankStateTrackerO(key)))
|
||||
}
|
||||
|
||||
class RankStateTrackerIO(val key: DramOrganizationParams) extends GenericParameterizedBundle(key)
|
||||
class RankStateTrackerIO(val key: DramOrganizationParams) extends Bundle
|
||||
with HasLegalityUpdateIO with HasDRAMMASConstants {
|
||||
val rank = new RankStateTrackerO(key)
|
||||
val tCycle = Input(UInt(maxDRAMTimingBits.W))
|
||||
|
|
@ -605,7 +604,7 @@ class CommandBusMonitor extends Module {
|
|||
}
|
||||
}
|
||||
|
||||
class RankRefreshUnitIO(key: DramOrganizationParams) extends GenericParameterizedBundle(key) {
|
||||
class RankRefreshUnitIO(val key: DramOrganizationParams) extends Bundle {
|
||||
val rankStati = Vec(key.maxRanks, Flipped(new RankStateTrackerO(key)))
|
||||
// The user may have instantiated multiple ranks, but is only modelling a single
|
||||
// rank system. Don't issue refreshes to ranks we aren't modelling
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
//See LICENSE for license details.
|
||||
//
|
||||
|
||||
package midas.passes
|
||||
|
||||
import midas.targetutils._
|
||||
|
|
|
|||
|
|
@ -2,11 +2,9 @@
|
|||
|
||||
package midas.passes
|
||||
|
||||
|
||||
import firrtl._
|
||||
import firrtl.ir._
|
||||
|
||||
|
||||
// Ensures that there are no dangling IO on the target. All I/O coming off the DUT must be bound
|
||||
// to an Bridge BlackBox
|
||||
case class TargetMalformedException(message: String) extends RuntimeException(message)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
|
||||
// See LICENSE for license details.
|
||||
|
||||
package midas.passes
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
//See LICENSE for license details.
|
||||
|
||||
package midas.passes
|
||||
|
||||
import firrtl.CircuitState
|
||||
|
|
|
|||
|
|
@ -3,11 +3,8 @@
|
|||
package midas
|
||||
package passes
|
||||
|
||||
|
||||
|
||||
import firrtl._
|
||||
|
||||
|
||||
private[midas] class MidasTransforms extends Transform {
|
||||
def inputForm = LowForm
|
||||
def outputForm = HighForm
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@ import firrtl.ir._
|
|||
import firrtl.Mappers._
|
||||
import firrtl.Utils.{zero, BoolType}
|
||||
|
||||
|
||||
import midas.passes.fame.{FAMEChannelConnectionAnnotation, WireChannel}
|
||||
import midas.widgets.{BridgeIOAnnotation, PrintBridgeModule, PrintBridgeParameters, PrintPort}
|
||||
import midas.targetutils.{SynthPrintfAnnotation, GlobalResetConditionSink}
|
||||
|
|
|
|||
|
|
@ -3,8 +3,6 @@
|
|||
package midas
|
||||
package passes
|
||||
|
||||
|
||||
|
||||
import firrtl._
|
||||
import firrtl.annotations.{CircuitName, ModuleTarget, InstanceTarget}
|
||||
import firrtl.options.Dependency
|
||||
|
|
@ -117,4 +115,3 @@ private[passes] class SimulationMapping(targetName: String) extends firrtl.Trans
|
|||
linkedState.copy(annotations = linkedState.annotations ++ generateHeaderAnnos(shim))
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@ import midas.widgets.{RationalClock}
|
|||
import firrtl._
|
||||
import firrtl.annotations._
|
||||
|
||||
|
||||
/**
|
||||
* [[ChannelClockInfoAnalysis]]'s output annotation. Maps channel global name
|
||||
* (See [[FAMEChannelConnectionAnnotation]] to a clock info class.
|
||||
|
|
|
|||
|
|
@ -9,8 +9,6 @@ import annotations._
|
|||
import firrtl.Utils.BoolType
|
||||
import firrtl.transforms.BlackBoxInlineAnno
|
||||
|
||||
|
||||
|
||||
package object passes {
|
||||
/**
|
||||
* A utility for keeping statements defining and connecting signals to a piece of hardware
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@ class AssertBridgeRecord(assertPortName: String, resetPortName: String, numAsser
|
|||
val asserts = Output(UInt(numAsserts.W))
|
||||
val underGlobalReset = Output(Bool())
|
||||
val elements = ListMap(assertPortName -> asserts, resetPortName -> underGlobalReset)
|
||||
override def cloneType = new AssertBridgeRecord(assertPortName, resetPortName, numAsserts).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
case class AssertBridgeParameters(assertPortName: String, resetPortName: String, assertMessages: Seq[String])
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@ class AutoCounterBundle(
|
|||
(triggerName, triggerEnable) +:
|
||||
(resetPortName, underGlobalReset) +:
|
||||
events):_*)
|
||||
override def cloneType = new AutoCounterBundle(eventMetadata, triggerName, resetPortName).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
case class AutoCounterParameters(eventMetadata: Seq[EventMetadata], triggerName: String, resetPortName: String)
|
||||
|
|
|
|||
|
|
@ -33,8 +33,6 @@ class HostPortIO[+T <: Data](private val targetPortProto: T) extends Record with
|
|||
|
||||
val elements = collection.immutable.ListMap(Seq("fromHost" -> fromHost, "toHost" -> toHost, "hBits" -> hBits):_*)
|
||||
|
||||
override def cloneType: this.type = new HostPortIO(targetPortProto).asInstanceOf[this.type]
|
||||
|
||||
private[midas] def getClock(): Clock = {
|
||||
val allTargetClocks = SimUtils.findClocks(targetPortProto)
|
||||
require(allTargetClocks.nonEmpty,
|
||||
|
|
|
|||
|
|
@ -180,7 +180,6 @@ class PeekPokeTokenizedIO(private val targetIO: PeekPokeTargetIO) extends Record
|
|||
val outs = targetOutputs.map({ case (field, name) => name -> InputChannel(field) })
|
||||
val ins = targetInputs.map({ case (field, name) => name -> OutputChannel(field) })
|
||||
override val elements = ListMap((ins ++ outs):_*)
|
||||
override def cloneType = new PeekPokeTokenizedIO(targetIO).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
object PeekPokeTokenizedIO {
|
||||
|
|
@ -210,7 +209,6 @@ class PeekPokeTargetIO(targetIO: Seq[(String, Data)]) extends Record {
|
|||
Seq("clock" -> clock) ++
|
||||
targetIO.map({ case (name, field) => name -> Flipped(chiselTypeOf(field)) })
|
||||
):_*)
|
||||
override def cloneType = new PeekPokeTargetIO(targetIO).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
class PeekPokeBridge(targetIO: Seq[(String, Data)]) extends BlackBox
|
||||
|
|
|
|||
|
|
@ -25,7 +25,6 @@ class PrintRecord(portType: firrtl.ir.BundleType, val formatString: String) exte
|
|||
val enable = Output(Bool())
|
||||
|
||||
val elements = ListMap((Seq("enable" -> enable) ++ args):_*)
|
||||
override def cloneType = new PrintRecord(portType, formatString).asInstanceOf[this.type]
|
||||
|
||||
// Gets the bit position of each argument after the record has been flattened to a UInt
|
||||
def argumentOffsets() = args.foldLeft(Seq(enable.getWidth))({
|
||||
|
|
@ -43,7 +42,6 @@ class PrintRecordBag(resetPortName: String, printPorts: Seq[(firrtl.ir.Port, Str
|
|||
})
|
||||
|
||||
val elements = ListMap(((resetPortName -> underGlobalReset) +: printRecords):_*)
|
||||
override def cloneType = new PrintRecordBag(resetPortName, printPorts).asInstanceOf[this.type]
|
||||
|
||||
// Generates a Bool indicating if at least one Printf has it's enable set on this cycle
|
||||
def hasEnabledPrint(): Bool = printRecords.map(_._2.enable).foldLeft(false.B)(_ || _) && !underGlobalReset
|
||||
|
|
|
|||
|
|
@ -31,7 +31,6 @@ object SerializationUtils {
|
|||
val inputPorts = inputs.map(field => field.name -> Input(field.regenType()))
|
||||
val outputPorts = outputs.map(field => field.name -> Output(field.regenType()))
|
||||
override val elements = immutable.ListMap((inputPorts ++ outputPorts):_*)
|
||||
override def cloneType = new RegeneratedTargetIO(inputs, outputs).asInstanceOf[this.type]
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@ DRIVER_CC := \
|
|||
$(driver_dir)/bridges/BridgeHarness.cc \
|
||||
$(driver_dir)/bridges/$(DESIGN).cc \
|
||||
$(testchipip_csrc_dir)/testchip_tsi.cc \
|
||||
$(testchipip_csrc_dir)/testchip_htif.cc \
|
||||
$(wildcard $(addprefix $(firesim_lib_dir)/, \
|
||||
bridges/uart.cc \
|
||||
bridges/tsibridge.cc \
|
||||
|
|
|
|||
|
|
@ -43,14 +43,16 @@ DRIVER_H = \
|
|||
$(shell find $(driver_dir) -name "*.h") \
|
||||
$(shell find $(firesim_lib_dir) -name "*.h") \
|
||||
$(DROMAJO_REQS) \
|
||||
$(TESTCHIPIP_CSRC_DIR)/testchip_tsi.h
|
||||
$(TESTCHIPIP_CSRC_DIR)/testchip_tsi.h \
|
||||
$(TESTCHIPIP_CSRC_DIR)/testchip_htif.h
|
||||
|
||||
DRIVER_CC = \
|
||||
$(addprefix $(driver_dir)/firesim/, $(addsuffix .cc, firesim_top)) \
|
||||
$(wildcard $(addprefix $(firesim_lib_dir)/, $(addsuffix .cc, bridges/* fesvr/* bridges/tracerv/*))) \
|
||||
$(RISCV)/lib/libfesvr.a \
|
||||
$(DROMAJO_LIB_DIR)/lib$(DROMAJO_LIB_NAME).a \
|
||||
$(TESTCHIPIP_CSRC_DIR)/testchip_tsi.cc
|
||||
$(TESTCHIPIP_CSRC_DIR)/testchip_tsi.cc \
|
||||
$(TESTCHIPIP_CSRC_DIR)/testchip_htif.cc
|
||||
|
||||
# Disable missing override warning for testchipip.
|
||||
TARGET_CXX_FLAGS += -g \
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ class PointerChaserDUT(implicit val p: Parameters) extends Module with HasNastiP
|
|||
|
||||
when (rFire && memoryIF.r.bits.last){
|
||||
resultValid := isFinalNode
|
||||
resultReg := resultReg + memoryIF.r.bits.data.asSInt()
|
||||
resultReg := resultReg + memoryIF.r.bits.data.asSInt
|
||||
}.elsewhen (doneFire) {
|
||||
resultValid := false.B
|
||||
resultReg := 0.S
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Subproject commit 336f225143590f9060ebe7101e96f235f96db985
|
||||
Subproject commit 65ed3c162cc3d57c19d19621803a830a5f867e97
|
||||
Loading…
Reference in New Issue