diff --git a/.github/actions/buildsetup/action.yml b/.github/actions/buildsetup/action.yml index 83dd1531..f621b483 100644 --- a/.github/actions/buildsetup/action.yml +++ b/.github/actions/buildsetup/action.yml @@ -5,7 +5,8 @@ runs: using: "composite" steps: - run: | - source /etc/profile.d/conda.sh + source /opt/conda/etc/profile.d/conda.sh + conda activate firesim ./build-setup.sh --skip-validate # All actions that run in a GH-hosted container source env.sh before # running their jobs. This ensures conda is in the runner's path, which diff --git a/.github/scripts/run-local-buildbitstreams.py b/.github/scripts/run-local-buildbitstreams.py index b60077e9..00a4fc2d 100755 --- a/.github/scripts/run-local-buildbitstreams.py +++ b/.github/scripts/run-local-buildbitstreams.py @@ -11,13 +11,13 @@ import argparse from ci_variables import ci_env -from typing import List +from typing import List, Tuple GH_REPO = 'firesim-public-bitstreams' GH_ORG = 'firesim' URL_PREFIX = f"https://raw.githubusercontent.com/{GH_ORG}/{GH_REPO}" -build_location = "/scratch/buildbot/fstmp" +shared_build_dir = "/scratch/buildbot/FIRESIM_BUILD_DIR" # taken from https://stackoverflow.com/questions/63427607/python-upload-files-directly-to-github-using-pygithub # IMPORTANT: only works for binary files! (i.e. tar.gz files) @@ -90,6 +90,8 @@ def run_local_buildbitstreams(): def modify_config_build(hwdb_entries_to_gen: List[str]) -> str: build_yaml = f"{manager_fsim_dir}/deploy/config_build.yaml" copy_build_yaml = f"{manager_fsim_dir}/deploy/config_build_{hash(tuple(hwdb_entries_to_gen))}.yaml" + + # comment out old lines build_yaml_lines = open(build_yaml).read().split("\n") with open(copy_build_yaml, "w") as byf: for line in build_yaml_lines: @@ -97,15 +99,25 @@ def run_local_buildbitstreams(): # comment out AWS specific lines byf.write("# " + line + '\n') elif 'default_build_dir:' in line: - byf.write(line.replace('null', build_location) + '\n') - elif len([True for hwdb_entry_to_gen in hwdb_entries_to_gen if (f"- {hwdb_entry_to_gen}" in line)]): - # remove comment - byf.write(line.replace("# ", '') + '\n') + byf.write(line.replace('null', shared_build_dir) + '\n') else: byf.write(line + '\n') + + # add new builds to run + build_yaml_lines = open(copy_build_yaml).read().split("\n") + with open(copy_build_yaml, "w") as byf: + for line in build_yaml_lines: + if "builds_to_run:" in line and not "#" in line: + byf.write(line + '\n') + start_space_idx = line.index('b') + for hwdb_to_gen in hwdb_entries_to_gen: + byf.write((' ' * (start_space_idx + 4)) + f"- {hwdb_to_gen}" + '\n') + else: + byf.write(line + '\n') + return copy_build_yaml - def add_host_list(build_yaml: str, hostlist: List[str]) -> str: + def add_host_list(build_yaml: str, hostlist: List[Tuple[str, bool, str]]) -> str: copy_build_yaml = f"{manager_fsim_dir}/deploy/config_build_{hash(tuple(hostlist))}.yaml" build_yaml_lines = open(build_yaml).read().split("\n") with open(copy_build_yaml, "w") as byf: @@ -113,8 +125,12 @@ def run_local_buildbitstreams(): if "build_farm_hosts:" in line and not "#" in line: byf.write(line + '\n') start_space_idx = line.index('b') - for host in hostlist: - byf.write((' ' * (start_space_idx + 4)) + f"- {host}" + '\n') + for host, use_unique, unique_build_dir in hostlist: + if use_unique: + byf.write((' ' * (start_space_idx + 4)) + f"- {host}:" + '\n') + byf.write((' ' * (start_space_idx + 8)) + f"override_build_dir: {unique_build_dir}" + '\n') + else: + byf.write((' ' * (start_space_idx + 4)) + f"- {host}" + '\n') elif '- localhost' in line and not '#' in line: byf.write("# " + line + '\n') else: @@ -204,25 +220,30 @@ def run_local_buildbitstreams(): sample_hwdb_file.write(content) sample_hwdb_file.truncate() - # could potentially use knight/ferry in the future (currently unused since they are currently overloaded) - hosts = { - ("localhost", "vitis:2022.1"), - ("jktgz", "vivado:2021.1"), - ("jktqos", "vivado:2021.1"), - ("firesim1", "vivado:2019.1"), - } + # priority == roughly the more powerful and available + # ipaddr, buildtool:version, use unique build dir, unique build dir path, priority (0 is highest)(unused by code but used to track which machine has most resources) + hosts = [ + ("buildbot1@a17", "vitis:2022.1", True, "/scratch/buildbot1/FIRESIM_BUILD_DIR", 0), + ( "harp", "vitis:2022.1", False, "", 2), + ("buildbot2@a17", "vitis:2021.1", True, "/scratch/buildbot2/FIRESIM_BUILD_DIR", 0), + ("buildbot3@a17", "vitis:2021.1", True, "/scratch/buildbot3/FIRESIM_BUILD_DIR", 0), + ("buildbot4@a17", "vitis:2021.1", True, "/scratch/buildbot4/FIRESIM_BUILD_DIR", 0), + ( "firesim1", "vitis:2021.1", False, "", 1), + ( "jktgz", "vivado:2023.1", False, "", 3), + ( "jktqos", "vivado:2023.1", False, "", 3), + ] def do_builds(batch_hwdbs): assert len(hosts) >= len(batch_hwdbs), f"Need at least {len(batch_hwdbs)} hosts to run builds" # map hwdb tuple to hosts hwdb_2_host = {} - for hwdb in batch_hwdbs: - buildtool_version = hwdb[2] - for host in hosts: - if host[1] == buildtool_version: - if not host[0] in hwdb_2_host.values(): - hwdb_2_host[hwdb[0]] = host[0] + for hwdb, platform, buildtool_version in batch_hwdbs: + for host_name, host_buildtool_version, host_use_unique, host_unique_build_dir, host_prio in hosts: + if host_buildtool_version == buildtool_version: + if not host_name in [h[0] for h in hwdb_2_host.values()]: + hwdb_2_host[hwdb] = (host_name, host_use_unique, host_unique_build_dir) + break assert len(hwdb_2_host) == len(batch_hwdbs), "Unable to map hosts to hwdb build" @@ -242,24 +263,31 @@ def run_local_buildbitstreams(): replace_in_hwdb(hwdb, link) # wipe old data - for host in hosts_ordered: - run(f"ssh {host} rm -rf {build_location}") + for host_name, host_use_unique, host_unique_build_dir in hosts_ordered: + if host_use_unique: + run(f"ssh {host_name} rm -rf {host_unique_build_dir}") + else: + run(f"ssh {host_name} rm -rf {shared_build_dir}") + + # note: next two statements can be duplicated to run different builds in phases + # i.e. run 4 agfis in 1st phase, then 6 in next + + # order of following list roughly corresponds to build host to use. + # i.e. if 1st hwdb in list wants a host with V0 of tools, it will get the 1st host with V0 of tools + # in the hosts list - # same order as in config_build.yaml # hwdb_entry_name, platform_name, buildtool:version batch_hwdbs_in = [ ("vitis_firesim_rocket_singlecore_no_nic", "vitis", "vitis:2022.1"), - ("alveo_u250_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u250", "vivado:2021.1"), - ("alveo_u250_firesim_gemmini_rocket_singlecore_no_nic", "xilinx_alveo_u250", "vivado:2021.1"), - ] - do_builds(batch_hwdbs_in) - - batch_hwdbs_in = [ ("nitefury_firesim_rocket_singlecore_no_nic", "rhsresearch_nitefury_ii", "vitis:2022.1"), - ("alveo_u200_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u200", "vivado:2021.1"), - ("alveo_u280_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u280", "vivado:2021.1"), - ("xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic", "xilinx_vcu118", "vivado:2019.1"), + + ("alveo_u250_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u250", "vitis:2021.1"), + ("alveo_u250_firesim_gemmini_rocket_singlecore_no_nic", "xilinx_alveo_u250", "vitis:2021.1"), + ("alveo_u200_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u200", "vitis:2021.1"), + ("alveo_u280_firesim_rocket_singlecore_no_nic", "xilinx_alveo_u280", "vitis:2021.1"), + + ("xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic", "xilinx_vcu118", "vivado:2023.1"), ] do_builds(batch_hwdbs_in) diff --git a/.github/workflows/config/release-notes.json b/.github/workflows/config/release-notes.json new file mode 100644 index 00000000..d6098d7b --- /dev/null +++ b/.github/workflows/config/release-notes.json @@ -0,0 +1,56 @@ +{ + "categories": [ + { + "title": "## Added", + "labels": ["changelog:added"] + }, + { + "title": "## Changed", + "labels": ["changelog:changed"] + }, + { + "title": "## Fixed", + "labels": ["changelog:fixed"] + }, + { + "title": "## Removed", + "labels": ["changelog:removed"] + }, + { + "title": "## Uncategorized", + "labels": [] + } + ], + "ignore_labels": [ + "changelog:omit" + ], + "sort": { + "order": "ASC", + "on_property": "mergedAt" + }, + "template": "${{CHANGELOG}}\n\n**Full Changelog:** ${{RELEASE_DIFF}}\n", + "pr_template": "- ${{TITLE}} (by @${{AUTHOR}} in ${{URL}})${{RELEASE_NOTES}}", + "empty_template": "- no changes", + "transformers": [ + { + "pattern": "", + "flags": "gus", + "target": "" + } + ], + "custom_placeholders": [ + { + "name": "RELEASE_NOTES", + "source": "BODY", + "transformer": { + "pattern": ".*#### Release Notes(?:[\n\\s]|(?:))*((?:\\S(?!!--)).*?)[\n\\s]*\n#.*", + "flags": "gus", + "target": "\n $1" + } + } + ], + "trim_values": false, + "max_tags_to_fetch": 200, + "max_pull_requests": 500, + "max_back_track_time_days": 365 +} diff --git a/.github/workflows/firesim-cleanup.yml b/.github/workflows/firesim-cleanup.yml index 5f8aec5c..18a7f3ed 100644 --- a/.github/workflows/firesim-cleanup.yml +++ b/.github/workflows/firesim-cleanup.yml @@ -11,9 +11,11 @@ defaults: env: PERSONAL_ACCESS_TOKEN: ${{ secrets.BARTENDER_PERSONAL_ACCESS_TOKEN }} GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID }} - AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY }} - AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION }} + AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID_08012023 }} + AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY_08012023 }} + AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION_08012023 }} + FIRESIM_PEM: ${{ secrets.FIRESIM_PEM_08012023 }} + FIRESIM_PEM_PUBLIC: ${{ secrets.FIRESIM_PEM_PUBLIC }} AZURE_CLIENT_ID: ${{ secrets.AZURE_CLIENT_ID }} AZURE_CLIENT_SECRET: ${{ secrets.AZURE_CLIENT_SECRET }} AZURE_TENANT_ID: ${{ secrets.AZURE_TENANT_ID }} @@ -22,8 +24,6 @@ env: AZURE_RESOURCE_GROUP: ${{ secrets.AZURE_RESOURCE_GROUP }} AZURE_CI_SUBNET_ID : ${{ secrets.AZURE_CI_SUBNET_ID }} AZURE_CI_NSG_ID : ${{ secrets.AZURE_CI_NSG_ID }} - FIRESIM_PEM: ${{ secrets.FIRESIM_PEM }} - FIRESIM_PEM_PUBLIC: ${{ secrets.FIRESIM_PEM_PUBLIC }} MANAGER_FIRESIM_LOCATION: "~/firesim" REMOTE_WORK_DIR: unused TERM: xterm-256-color diff --git a/.github/workflows/firesim-publish-scala-doc.yml b/.github/workflows/firesim-publish-scala-doc.yml index befd2641..4bc42103 100644 --- a/.github/workflows/firesim-publish-scala-doc.yml +++ b/.github/workflows/firesim-publish-scala-doc.yml @@ -20,10 +20,10 @@ defaults: env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID }} - AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY }} - AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION }} - FIRESIM_PEM: ${{ secrets.FIRESIM_PEM }} + AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID_08012023 }} + AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY_08012023 }} + AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION_08012023 }} + FIRESIM_PEM: ${{ secrets.FIRESIM_PEM_08012023 }} FIRESIM-REPO-DEP-KEY: ${{ secrets.BARTENDER_PRIVATE_SSH_KEY }} MANAGER_FIRESIM_LOCATION: "~/firesim" LANG: "en_US.UTF-8" # required by SBT when it sees boost directories @@ -53,16 +53,7 @@ jobs: needs: change-filters if: needs.change-filters.outputs.needs-scala-doc == 'true' runs-on: ubuntu-20.04 - container: - image: firesim/firesim-ci:v1.3 - options: --entrypoint /bin/bash - env: - JAVA_HEAP_SIZE: 3500M # Default JVM maximum heap limit steps: - - run: | - sudo yum -y remove git git224 git224-core ius-release.noarch # remove any older git versions and collateral first from docker image - sudo yum -y install https://repo.ius.io/ius-release-el7.rpm # re-install for now - sudo yum -y install git236 # install working git version (must match machine-launch) - uses: actions/checkout@v3 - uses: ./.github/actions/repo-setup - uses: ./.github/actions/build-scala-doc diff --git a/.github/workflows/firesim-run-tests.yml b/.github/workflows/firesim-run-tests.yml index 3b0115d7..cb0626d2 100644 --- a/.github/workflows/firesim-run-tests.yml +++ b/.github/workflows/firesim-run-tests.yml @@ -14,9 +14,11 @@ defaults: env: PERSONAL_ACCESS_TOKEN: ${{ secrets.BARTENDER_PERSONAL_ACCESS_TOKEN }} GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} - AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID }} - AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY }} - AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION }} + AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID_08012023 }} + AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY_08012023 }} + AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION_08012023 }} + FIRESIM_PEM: ${{ secrets.FIRESIM_PEM_08012023 }} + FIRESIM_PEM_PUBLIC: ${{ secrets.FIRESIM_PEM_PUBLIC }} AZURE_CLIENT_ID: ${{ secrets.AZURE_CLIENT_ID }} AZURE_CLIENT_SECRET: ${{ secrets.AZURE_CLIENT_SECRET }} AZURE_TENANT_ID: ${{ secrets.AZURE_TENANT_ID }} @@ -25,8 +27,6 @@ env: AZURE_RESOURCE_GROUP: ${{ secrets.AZURE_RESOURCE_GROUP }} AZURE_CI_SUBNET_ID : ${{ secrets.AZURE_CI_SUBNET_ID }} AZURE_CI_NSG_ID : ${{ secrets.AZURE_CI_NSG_ID }} - FIRESIM_PEM: ${{ secrets.FIRESIM_PEM }} - FIRESIM_PEM_PUBLIC: ${{ secrets.FIRESIM_PEM_PUBLIC }} MANAGER_FIRESIM_LOCATION: "~/firesim" LANG: "en_US.UTF-8" # required by SBT when it sees boost directories LANGUAGE: "en_US:en" diff --git a/.github/workflows/release-notes.yml b/.github/workflows/release-notes.yml new file mode 100644 index 00000000..ce047d5f --- /dev/null +++ b/.github/workflows/release-notes.yml @@ -0,0 +1,51 @@ +# adapted from https://github.com/chipsalliance/chisel/blob/main/.github/workflows/release-notes.yml + +name: Generate Release Notes + +on: + release: + types: [created] + workflow_dispatch: + inputs: + toTag: + description: 'Tag or ref for which to generate release notes' + required: true + fromTag: + # If you leave this blank, it'll select previous SemVer version + # WARNING: Cannot use anything older than a005498 because of the git tree merge + description: 'Tag or ref from which to start generating release notes' + required: false + + +jobs: + generate_release_notes: + name: Generate Release Notes + runs-on: ubuntu-latest + + steps: + - name: Checkout + uses: actions/checkout@v3 + - name: Build Release Notes + id: release-notes + uses: mikepenz/release-changelog-builder-action@v3.7.0 + with: + configuration: .github/workflows/config/release-notes.json + failOnError: true + # Amazingly, on release where the inputs are empty, this just does the right thing + # The "toTag" is the released tag, and the "fromTag" is the previous tag according to SemVer + fromTag: ${{ github.event.inputs.fromTag }} + toTag: ${{ github.event.inputs.toTag }} + token: ${{ secrets.GITHUB_TOKEN }} + - name: Report Release Notes + # Put output through env variable to make it robust to quotes + env: + CHANGELOG: ${{steps.release-notes.outputs.changelog}} + run: echo "$CHANGELOG" >> $GITHUB_STEP_SUMMARY + - name: Upload Release Notes (on release) + if: github.event_name == 'release' + uses: softprops/action-gh-release@v0.1.15 + with: + body: ${{ steps.release-notes.outputs.changelog }} + - name: Error on uncategorized PRs + if: steps.release-notes.outputs.uncategorized_prs != 0 + run: exit 1 diff --git a/.github/workflows/require-label.yml b/.github/workflows/require-label.yml new file mode 100644 index 00000000..0088f6bd --- /dev/null +++ b/.github/workflows/require-label.yml @@ -0,0 +1,24 @@ +# adapted from https://github.com/chipsalliance/chisel/blob/main/.github/workflows/require-label.yml + +name: Require Release Notes Label + +on: + pull_request: + branches: + - main + types: + - opened + - synchronize + - reopened + - labeled + - unlabeled + +jobs: + check_labels: + name: Check Labels + runs-on: ubuntu-latest + steps: + - uses: docker://agilepathway/pull-request-label-checker:v1.4.25 + with: + one_of: changelog:added,changelog:changed,changelog:fixed,changelog:omit,changelog:removed + repo_token: ${{ secrets.GITHUB_TOKEN }} diff --git a/CHANGELOG.md b/CHANGELOG.md index 09fceb77..e0fafd4c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,23 @@ This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/ +## [1.17.1] - 2023-07-14 +Fix missing mcs file in VCU118 bitstream_tar. Automatically generate release notes for faster releases. CI improvements. + +### Added +- Bucket log docs (by @joey0320 in https://github.com/firesim/firesim/pull/1575) +- Add release note automation (by @abejgonzalez in https://github.com/firesim/firesim/pull/1595) + +### Changed +- Use bar-tender specific access (by @abejgonzalez in https://github.com/firesim/firesim/pull/1558) +- CI modifications - Support Vivado 2022.1, New CI machine(s) (by @abejgonzalez in https://github.com/firesim/firesim/pull/1592) + +### Fixed +- Fix VCU118 bitstream_tar missing mcs file (by @abejgonzalez in https://github.com/firesim/firesim/pull/1592) +- Additional VCU118 initial setup fixes (by @sagark in https://github.com/firesim/firesim/pull/1606) + +**Full Changelog:** https://github.com/firesim/firesim/compare/1.17.0...main + ## [1.17.0] - 2023-06-16 Support for several new local FPGA boards added: Xilinx VCU118 (w/XDMA), Xilinx Alveo U250/U280 (w/XDMA, in addition to previous Vitis support), RHSResearch NiteFury II (w/XDMA). FireSim now also supports Xcelium for metasims. diff --git a/build-setup-nolog.sh b/build-setup-nolog.sh index 401ead96..1f4b872b 100644 --- a/build-setup-nolog.sh +++ b/build-setup-nolog.sh @@ -142,7 +142,7 @@ else ./scripts/generate-conda-lockfile.sh fi LOCKFILE="$(find $RDIR/conda-reqs/*.conda-lock.yml)" - conda-lock install -p $RDIR/.conda-env $LOCKFILE + conda-lock install --conda $(which conda) -p $RDIR/.conda-env $LOCKFILE source $RDIR/.conda-env/etc/profile.d/conda.sh conda activate $RDIR/.conda-env env_append "$CONDA_ACTIVATE_PREAMBLE" diff --git a/conda-reqs/conda-reqs.conda-lock.yml b/conda-reqs/conda-reqs.conda-lock.yml index 09e9e136..d3fe3505 100644 --- a/conda-reqs/conda-reqs.conda-lock.yml +++ b/conda-reqs/conda-reqs.conda-lock.yml @@ -9,7 +9,7 @@ # To update a single package to the latest version compatible with the version constraints in the source: # conda-lock lock --lockfile conda-reqs.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /scratch/abejgonza/firesim/conda-reqs/firesim.yaml -f /scratch/abejgonza/firesim/conda-reqs/ci-shared.yaml -f /scratch/abejgonza/fs-typing/conda-reqs/firesim.yaml -f /scratch/abejgonza/fs-typing/conda-reqs/ci-shared.yaml -f /scratch/abejgonza/al2-fs/conda-reqs/firesim.yaml -f /scratch/abejgonza/al2-fs/conda-reqs/ci-shared.yaml -f /scratch/abejgonza/fs-buildafi-ci/conda-reqs/firesim.yaml -f /scratch/abejgonza/fs-buildafi-ci/conda-reqs/ci-shared.yaml -f /scratch/abejgonza/cy-check/sims/firesim/conda-reqs/firesim.yaml -f /scratch/abejgonza/cy-check/sims/firesim/conda-reqs/ci-shared.yaml -f /scratch/abejgonza/fs-rcbump/conda-reqs/firesim.yaml -f /scratch/abejgonza/fs-rcbump/conda-reqs/ci-shared.yaml --lockfile conda-reqs.conda-lock.yml +# conda-lock -f /scratch/abejgonza/firesim/conda-reqs/firesim.yaml -f /scratch/abejgonza/firesim/conda-reqs/ci-shared.yaml -f /scratch/abejgonza/fs-typing/conda-reqs/firesim.yaml -f /scratch/abejgonza/fs-typing/conda-reqs/ci-shared.yaml -f /scratch/abejgonza/al2-fs/conda-reqs/firesim.yaml -f /scratch/abejgonza/al2-fs/conda-reqs/ci-shared.yaml -f /scratch/abejgonza/fs-buildafi-ci/conda-reqs/firesim.yaml -f /scratch/abejgonza/fs-buildafi-ci/conda-reqs/ci-shared.yaml -f /scratch/abejgonza/cy-check/sims/firesim/conda-reqs/firesim.yaml -f /scratch/abejgonza/cy-check/sims/firesim/conda-reqs/ci-shared.yaml -f /scratch/abejgonza/fs-rcbump/conda-reqs/firesim.yaml -f /scratch/abejgonza/fs-rcbump/conda-reqs/ci-shared.yaml -f /scratch/abejgonza/new-cy/sims/firesim/conda-reqs/firesim.yaml -f /scratch/abejgonza/new-cy/sims/firesim/conda-reqs/ci-shared.yaml -f /scratch/abejgonza/fs-bump-vivado/conda-reqs/firesim.yaml -f /scratch/abejgonza/fs-bump-vivado/conda-reqs/ci-shared.yaml --lockfile conda-reqs.conda-lock.yml metadata: channels: - url: conda-forge @@ -19,7 +19,7 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: 71c8fd7b314d91d449dcb72854671e3c751c788e69fc879d5d96313909880024 + linux-64: dd2c20d18653250bbb1aa7ea8b364a8b51b849d07de34ca5465d9cd56610f7b1 platforms: - linux-64 sources: @@ -35,6 +35,10 @@ metadata: - /scratch/abejgonza/cy-check/sims/firesim/conda-reqs/ci-shared.yaml - /scratch/abejgonza/fs-rcbump/conda-reqs/firesim.yaml - /scratch/abejgonza/fs-rcbump/conda-reqs/ci-shared.yaml + - /scratch/abejgonza/new-cy/sims/firesim/conda-reqs/firesim.yaml + - /scratch/abejgonza/new-cy/sims/firesim/conda-reqs/ci-shared.yaml + - /scratch/abejgonza/fs-bump-vivado/conda-reqs/firesim.yaml + - /scratch/abejgonza/fs-bump-vivado/conda-reqs/ci-shared.yaml package: - category: main dependencies: {} @@ -72,14 +76,14 @@ package: - category: main dependencies: {} hash: - md5: f5c65075fc34438d5b456c7f3f5ab695 - sha256: 0cf1bb3d0bfc5519b60af2c360fa4888fb838e1476b1e0f65b9dbc48b45c7345 + md5: a73ecd2988327ad4c8f2c331482917f2 + sha256: 525b7b6b5135b952ec1808de84e5eca57c7c7ff144e29ef3e96ae4040ff432c1 manager: conda name: ca-certificates optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/ca-certificates-2023.5.7-hbcca054_0.conda - version: 2023.5.7 + url: https://conda.anaconda.org/conda-forge/linux-64/ca-certificates-2023.7.22-hbcca054_0.conda + version: 2023.7.22 - category: main dependencies: {} hash: @@ -149,47 +153,47 @@ package: - category: main dependencies: {} hash: - md5: 199a7292b1d3535376ecf7670c231d1f - sha256: d6df7758b85d4f82baaa526bff1b9f0a9ae2b73b0df7fcb27cafdaf5e24fdefb + md5: b9ae31bc2e565684ebaf82d4bd954d55 + sha256: 257495088b78d4344c7ea21145581ed6da1c5bf8320f49b659ce2ed2d6265f76 manager: conda name: libgcc-devel_linux-64 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libgcc-devel_linux-64-12.2.0-h3b97bd3_19.tar.bz2 - version: 12.2.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libgcc-devel_linux-64-12.3.0-h8bca6fd_0.conda + version: 12.3.0 - category: main dependencies: {} hash: - md5: 164b4b1acaedc47ee7e658ae6b308ca3 - sha256: 03ea784edd12037dc3a7a0078ff3f9c3383feabb34d5ba910bb2fd7a21a2d961 + md5: afb656a334c409dd9805508af1c89c7a + sha256: a06235f4c4b85b463d9b8a73c9e10c1b5b4105f8a0ea8ac1f2f5f64edac3dfe7 manager: conda name: libgfortran5 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libgfortran5-12.2.0-h337968e_19.tar.bz2 - version: 12.2.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libgfortran5-13.1.0-h15d22d2_0.conda + version: 13.1.0 - category: main dependencies: {} hash: - md5: 277d373b57791ee71cafc3c5bfcf0641 - sha256: 152a54b52b0bc0cda89b4394e43f010ce2a16f4012a3e706709d53a68407df46 + md5: 7c80158949230e6d837186b20b2fcf13 + sha256: b311dad92ffafd29668fca6330dc707f4d7f154a4fa4c3859832897416de39ec manager: conda name: libstdcxx-devel_linux-64 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libstdcxx-devel_linux-64-12.2.0-h3b97bd3_19.tar.bz2 - version: 12.2.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libstdcxx-devel_linux-64-12.3.0-h8bca6fd_0.conda + version: 12.3.0 - category: main dependencies: {} hash: - md5: 1030b1f38c129f2634eae026f704fe60 - sha256: 0289e6a7b9a5249161a3967909e12dcfb4ab4475cdede984635d3fb65c606f08 + md5: 067bcc23164642f4c226da631f2a2e1d + sha256: 6f9eb2d7a96687938c0001166a3b308460a8eb02b10e9d0dd9e251f0219ea05c manager: conda name: libstdcxx-ng optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libstdcxx-ng-12.2.0-h46fd767_19.tar.bz2 - version: 12.2.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libstdcxx-ng-13.1.0-hfd8a6a1_0.conda + version: 13.1.0 - category: main dependencies: {} hash: @@ -241,28 +245,28 @@ package: version: 3.10.0 - category: main dependencies: - libgfortran5: 12.2.0 h337968e_19 + libgfortran5: 13.1.0 h15d22d2_0 hash: - md5: cd7a806282c16e1f2d39a7e80d3a3e0d - sha256: c7d061f323e80fbc09564179073d8af303bf69b953b0caddcf79b47e352c746f + md5: 506dc07710dd5b0ba63cbf134897fc10 + sha256: 429e1d8a3e70b632df5b876e3fc322a56f769756693daa07114c46fa5098684e manager: conda name: libgfortran-ng optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libgfortran-ng-12.2.0-h69a702a_19.tar.bz2 - version: 12.2.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libgfortran-ng-13.1.0-h69a702a_0.conda + version: 13.1.0 - category: main dependencies: _libgcc_mutex: 0.1 conda_forge hash: - md5: cedcee7c064c01c403f962c9e8d3c373 - sha256: 81a76d20cfdee9fe0728b93ef057ba93494fd1450d42bc3717af4e468235661e + md5: 56ca14d57ac29a75d23a39eb3ee0ddeb + sha256: 5d441d80b57f857ad305a65169a6b915d4fd6735cdc9e9bded35d493c91ef16d manager: conda name: libgomp optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libgomp-12.2.0-h65d4601_19.tar.bz2 - version: 12.2.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libgomp-13.1.0-he5830b7_0.conda + version: 13.1.0 - category: main dependencies: _libgcc_mutex: 0.1 conda_forge @@ -319,14 +323,14 @@ package: _libgcc_mutex: 0.1 conda_forge _openmp_mutex: '>=4.5' hash: - md5: e4c94f80aef025c17ab0828cd85ef535 - sha256: f3899c26824cee023f1e360bd0859b0e149e2b3e8b1668bc6dd04bfc70dcd659 + md5: cd93f779ff018dd85c7544c015c9db3c + sha256: fba897a02f35b2b5e6edc43a746d1fa6970a77b422f258246316110af8966911 manager: conda name: libgcc-ng optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libgcc-ng-12.2.0-h65d4601_19.tar.bz2 - version: 12.2.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libgcc-ng-13.1.0-he5830b7_0.conda + version: 13.1.0 - category: main dependencies: libgcc-ng: '>=12' @@ -566,25 +570,25 @@ package: libgcc-ng: '>=12' libstdcxx-ng: '>=12' hash: - md5: f67106643beadfc737b94ca0bfd6d8e3 - sha256: 1778dc86603df24aaf6865f7f3e1ffc5c793a0f1fc4570add2a6ccb4c0a62785 + md5: d1db1b8be7c3a8983dcbbbfe4f0765de + sha256: 3c6fab31ed4dc8428605588454596b307b1bd59d33b0c7073c407ab51408b011 manager: conda name: libabseil optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libabseil-20230125.2-cxx17_h59595ed_2.conda - version: '20230125.2' + url: https://conda.anaconda.org/conda-forge/linux-64/libabseil-20230125.3-cxx17_h59595ed_0.conda + version: '20230125.3' - category: main dependencies: libgcc-ng: '>=12' hash: - md5: 9194c9bf9428035a05352d031462eae4 - sha256: ddc961a36d498aaafd5b71078836ad5dd247cc6ba7924157f3801a2f09b77b14 + md5: 61641e239f96eae2b8492dc7e755828c + sha256: fc57c0876695c5b4ab7173438580c1d7eaa7dccaf14cb6467ca9e0e97abe0cf0 manager: conda name: libbrotlicommon optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libbrotlicommon-1.0.9-h166bdaf_8.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/libbrotlicommon-1.0.9-h166bdaf_9.conda version: 1.0.9 - category: main dependencies: @@ -686,28 +690,28 @@ package: dependencies: libgcc-ng: '>=12' libgfortran-ng: '' - libgfortran5: '>=10.4.0' + libgfortran5: '>=11.3.0' hash: - md5: 8c5963a49b6035c40646a763293fbb35 - sha256: 018372af663987265cb3ca8f37ac8c22b5f39219f65a0c162b056a30af11bba0 + md5: 9c5ea51ccb8ffae7d06c645869d24ce6 + sha256: 00aee12d04979d024c7f9cabccff5f5db2852c934397ec863a4abde3e09d5a79 manager: conda name: libopenblas optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libopenblas-0.3.21-pthreads_h78a6416_3.tar.bz2 - version: 0.3.21 + url: https://conda.anaconda.org/conda-forge/linux-64/libopenblas-0.3.23-pthreads_h80387f5_0.conda + version: 0.3.23 - category: main dependencies: - libgcc-ng: '>=12.2.0' + libgcc-ng: '>=12.3.0' hash: - md5: 80d0e00150401e9c06a055f36e8e73f2 - sha256: 6cf904606c091e1cab5cf3b1f1bb0d6756474e6e37b1a97a502fc1255d71641b + md5: bbc8fef17925480272a671b1d83431fa + sha256: 2fa38e53f7d58789283af351f014748a485ec8f4e7db3f150ed6274f50983663 manager: conda name: libsanitizer optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libsanitizer-12.2.0-h46fd767_19.tar.bz2 - version: 12.2.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libsanitizer-12.3.0-h0f45ef3_0.conda + version: 12.3.0 - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -772,37 +776,37 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: e5cb4fe581a18ca2185a016eb848fc00 - sha256: dc14922a6d5cf7fde55c0aa8f6661d6871c6a2e94369e7455a8a5927c3065080 + md5: d5447f6f8c208232db63db85e053574d + sha256: 4910371113afddc55b9a70f468e0c921600ff76e2e5da4084e6039f685ab8151 manager: conda name: libuv optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libuv-1.44.2-h166bdaf_0.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/libuv-1.44.2-hd590300_1.conda version: 1.44.2 - category: main dependencies: libgcc-ng: '>=12' hash: - md5: 0d4a7508d8c6c65314f2b9c1f56ad408 - sha256: ac3e073ea77803da71eb77e7fcef07defb345bda95eee3327c73ddf85b5714da + md5: 82bf6f63eb15ef719b556b63feec3a77 + sha256: 66658d5cdcf89169e284488d280b6ce693c98c0319d7eabebcedac0929140a73 manager: conda name: libwebp-base optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-base-1.3.0-h0b41bf4_0.conda - version: 1.3.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-base-1.3.1-hd590300_0.conda + version: 1.3.1 - category: main dependencies: libgcc-ng: '>=12' hash: - md5: f3f9de449d32ca9b9c66a22863c96f41 - sha256: 22f3663bcf294d349327e60e464a51cd59664a71b8ed70c28a9f512d10bc77dd + md5: f36c115f1ee199da648e0597ec2047ad + sha256: 370c7c5893b737596fd6ca0d9190c9715d89d888b8c88537ae1ef168c25e82e4 manager: conda name: libzlib optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libzlib-1.2.13-h166bdaf_4.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/libzlib-1.2.13-hd590300_5.conda version: 1.2.13 - category: main dependencies: @@ -855,16 +859,16 @@ package: version: '4.3' - category: main dependencies: - libgcc-ng: '>=10.3.0' + libgcc-ng: '>=12' hash: - md5: 4acfc691e64342b9dae57cf2adc63238 - sha256: b801e8cf4b2c9a30bce5616746c6c2a4e36427f045b46d9fc08a4ed40a9f7065 + md5: 681105bccc2a3f7f1a837d47d39c9179 + sha256: ccf61e61d58a8a7b2d66822d5568e2dc9387883dd9b2da61e1d787ece4c4979a manager: conda name: ncurses optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/ncurses-6.3-h27087fc_1.tar.bz2 - version: '6.3' + url: https://conda.anaconda.org/conda-forge/linux-64/ncurses-6.4-hcb278e6_0.conda + version: '6.4' - category: main dependencies: libgcc-ng: '>=12' @@ -930,13 +934,13 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: 0bcb0ab6faa796a22b40de3a41e3b2de - sha256: 3f7e1e46d0967f8d08026116aa84fda07bc93d11d44dc3c03a29ad9d3ffc63cc + md5: 899f432216154b3c60164667c1c598a0 + sha256: 737b7024a8ba17eb1c6740b7752b2064ede61905dd0b443415b145fb1f5b6739 manager: conda name: rhash optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/rhash-1.4.3-h166bdaf_0.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/rhash-1.4.3-hd590300_1.conda version: 1.4.3 - category: main dependencies: @@ -1000,16 +1004,16 @@ package: version: 1.0.7 - category: main dependencies: - libgcc-ng: '>=9.3.0' + libgcc-ng: '>=12' hash: - md5: d6b0b50b49eccfe0be0373be628be0f3 - sha256: f15ce1dff16823888bcc2be1738aadcb36699be1e2dd2afa347794c7ec6c1587 + md5: b462a33c0be1421532f28bfe8f4a7514 + sha256: 5aa9b3682285bb2bf1a8adc064cb63aff76ef9178769740d855abb42b0d24236 manager: conda name: xorg-libice optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libice-1.0.10-h7f98852_0.tar.bz2 - version: 1.0.10 + url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libice-1.1.1-hd590300_0.conda + version: 1.1.1 - category: main dependencies: libgcc-ng: '>=12' @@ -1188,58 +1192,58 @@ package: - category: main dependencies: binutils_impl_linux-64: '>=2.39' - libgcc-devel_linux-64: 12.2.0 h3b97bd3_19 - libgcc-ng: '>=12.2.0' - libgomp: '>=12.2.0' - libsanitizer: 12.2.0 h46fd767_19 - libstdcxx-ng: '>=12.2.0' + libgcc-devel_linux-64: 12.3.0 h8bca6fd_0 + libgcc-ng: '>=12.3.0' + libgomp: '>=12.3.0' + libsanitizer: 12.3.0 h0f45ef3_0 + libstdcxx-ng: '>=12.3.0' sysroot_linux-64: '' hash: - md5: bb48ea333c8e6dcc159a1575f04d869e - sha256: 1e67063ca887c0569c647d7e8e3da9d09234585ed0fce7f728d6709d7314d0f5 + md5: 1e41f51d89695fd3f810e2245517460b + sha256: ccbbb82de1ca95b02477e4340c5791e49424b379c6caa27e89bae3c40b7ad296 manager: conda name: gcc_impl_linux-64 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gcc_impl_linux-64-12.2.0-hcc96c02_19.tar.bz2 - version: 12.2.0 + url: https://conda.anaconda.org/conda-forge/linux-64/gcc_impl_linux-64-12.3.0-he2b93b0_0.conda + version: 12.3.0 - category: main dependencies: - libopenblas: '>=0.3.21,<1.0a0' + libopenblas: '>=0.3.23,<1.0a0' hash: - md5: d9b7a8639171f6c6fa0a983edabcfe2b - sha256: 4e4c60d3fe0b95ffb25911dace509e3532979f5deef4364141c533c5ca82dd39 + md5: 57fb44770b1bc832fb2dbefa1bd502de + sha256: 5a9dfeb9ede4b7ac136ac8c0b589309f8aba5ce79d14ca64ad8bffb3876eb04b manager: conda name: libblas optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libblas-3.9.0-16_linux64_openblas.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/libblas-3.9.0-17_linux64_openblas.conda version: 3.9.0 - category: main dependencies: - libbrotlicommon: 1.0.9 h166bdaf_8 + libbrotlicommon: 1.0.9 h166bdaf_9 libgcc-ng: '>=12' hash: - md5: 4ae4d7795d33e02bd20f6b23d91caf82 - sha256: d88ba07c3be27c89cb4975cc7edf63ee7b1c62d01f70d5c3f7efeb987c82b052 + md5: 081aa22f4581c08e4372b0b6c2f8478e + sha256: 564f301430c3c61bc5e149e74157ec181ed2a758befc89f7c38466d515a0f614 manager: conda name: libbrotlidec optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libbrotlidec-1.0.9-h166bdaf_8.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/libbrotlidec-1.0.9-h166bdaf_9.conda version: 1.0.9 - category: main dependencies: - libbrotlicommon: 1.0.9 h166bdaf_8 + libbrotlicommon: 1.0.9 h166bdaf_9 libgcc-ng: '>=12' hash: - md5: 04bac51ba35ea023dc48af73c1c88c25 - sha256: a0468858b2f647f51509a32040e93512818a8f9980f20b3554cccac747bcc4be + md5: 1f0a03af852a9659ed2bf08f2f1704fd + sha256: d27bc2562ea3f3b2bfd777f074f1cac6bfa4a737233dad288cd87c4634a9bb3a manager: conda name: libbrotlienc optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libbrotlienc-1.0.9-h166bdaf_8.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/libbrotlienc-1.0.9-h166bdaf_9.conda version: 1.0.9 - category: main dependencies: @@ -1318,14 +1322,14 @@ package: libstdcxx-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: 498393f87a3979b097e4c14d9c53438a - sha256: ea98b575ac097670bc3179389322967c9da3e67adc30ffa2cff8d4a70f9a19a2 + md5: c8da7f04073ed0fabcb60885a4c1a722 + sha256: b0255d3c46c71e184d0513566a770356abf2cede5e795c4944521c4f7b6a26d4 manager: conda name: libprotobuf optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libprotobuf-4.23.2-hd1fb520_2.conda - version: 4.23.2 + url: https://conda.anaconda.org/conda-forge/linux-64/libprotobuf-4.23.3-hd1fb520_0.conda + version: 4.23.3 - category: main dependencies: libgcc-ng: '>=12' @@ -1342,17 +1346,17 @@ package: - category: main dependencies: libgcc-ng: '>=12' - libzlib: '>=1.2.12,<1.3.0a0' - openssl: '>=3.0.5,<4.0a0' + libzlib: '>=1.2.13,<1.3.0a0' + openssl: '>=3.1.1,<4.0a0' hash: - md5: d85acad4b47dff4e3def14a769a97906 - sha256: 9a9a01f35d2d50326eb8ca7c0a92d0c45b2d0f77d9ea117680c70094ff480c0c + md5: 1f5a58e686b13bcfde88b93f547d23fe + sha256: 50e47fd9c4f7bf841a11647ae7486f65220cfc988ec422a4475fe8d5a823824d manager: conda name: libssh2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libssh2-1.10.0-hf14f497_3.tar.bz2 - version: 1.10.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libssh2-1.11.0-h0841786_0.conda + version: 1.11.0 - category: main dependencies: libgcc-ng: '>=12' @@ -1440,16 +1444,16 @@ package: version: '10.40' - category: main dependencies: - libgcc-ng: '>=9.4.0' + libgcc-ng: '>=12' libnsl: '>=2.0.0,<2.1.0a0' hash: - md5: 09ba115862623f00962e9809ea248f1a - sha256: a116c1d3c64a072280b441c43d893d341a1d37d16ec18afc76eee40299deabfa + md5: 3e785bff761095eb7f8676f4694bd1b1 + sha256: 6e18c1488d191cb1a43a483f44fffa75668779a29927319b4adeb10da12ad06b manager: conda name: perl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/perl-5.32.1-2_h7f98852_perl5.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/perl-5.32.1-4_hd590300_perl5.conda version: 5.32.1 - category: main dependencies: @@ -1531,30 +1535,30 @@ package: version: '5.0' - category: main dependencies: - libgcc-ng: '>=9.3.0' - libuuid: '>=2.32.1,<3.0a0' - xorg-libice: 1.0.* + libgcc-ng: '>=12' + libuuid: '>=2.38.1,<3.0a0' + xorg-libice: '>=1.1.1,<2.0a0' hash: - md5: 9e856f78d5c80d5a78f61e72d1d473a3 - sha256: bdb350539521ddc1f30cc721b6604eced8ef72a0ec146e378bfe89e2be17ab35 + md5: 93ee23f12bc2e684548181256edd2cf6 + sha256: 089ad5f0453c604e18985480218a84b27009e9e6de9a0fa5f4a20b8778ede1f1 manager: conda name: xorg-libsm optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libsm-1.2.3-hd9c2040_1000.tar.bz2 - version: 1.2.3 + url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libsm-1.2.4-h7391055_0.conda + version: 1.2.4 - category: main dependencies: libgcc-ng: '>=12' - libzlib: 1.2.13 h166bdaf_4 + libzlib: 1.2.13 hd590300_5 hash: - md5: 4b11e365c0275b808be78b30f904e295 - sha256: 282ce274ebe6da1fbd52efbb61bd5a93dec0365b14d64566e6819d1691b75300 + md5: 68c34ec6149623be41a1933ab996a209 + sha256: 9887a04d7e7cb14bd2b52fa01858f05a6d7f002c890f618d9fcd864adbfecb1b manager: conda name: zlib optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/zlib-1.2.13-h166bdaf_4.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/zlib-1.2.13-hd590300_5.conda version: 1.2.13 - category: main dependencies: @@ -1562,14 +1566,28 @@ package: libstdcxx-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: 6b63daed8feeca47be78f323e793d555 - sha256: fbe49a8c8df83c2eccb37c5863ad98baeb29796ec96f2c503783d7b89bf80c98 + md5: 32ae18eb2a687912fc9e92a501c0a11b + sha256: a7f7e765dfb7af5265a38080e46f18cb07cfeecf81fe28fad23c4538e7d521c3 manager: conda name: zstd optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/zstd-1.5.2-h3eb15da_6.conda + url: https://conda.anaconda.org/conda-forge/linux-64/zstd-1.5.2-hfc55251_7.conda version: 1.5.2 +- category: main + dependencies: + libgcc-ng: '>=12' + m4: '' + perl: 5.* + hash: + md5: 50cabb1aee157a18082c7c92cc4b3143 + sha256: 04868bf7a2737af8c8a828b2c4b59653180a91da9c3ece77bae4e429a1b84cc1 + manager: conda + name: autoconf + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/autoconf-2.71-pl5321h2b4cb7a_1.conda + version: '2.71' - category: main dependencies: libgcc-ng: '>=12' @@ -1599,30 +1617,30 @@ package: version: 3.8.2 - category: main dependencies: - libbrotlidec: 1.0.9 h166bdaf_8 - libbrotlienc: 1.0.9 h166bdaf_8 + libbrotlidec: 1.0.9 h166bdaf_9 + libbrotlienc: 1.0.9 h166bdaf_9 libgcc-ng: '>=12' hash: - md5: e5613f2bc717e9945840ff474419b8e4 - sha256: ab1994e03bdd88e4b27f9f802ac18e45ed29b92cce25e1fd86da43b89734950f + md5: d47dee1856d9cb955b8076eeff304a5b + sha256: 1c128f136a59ee2fa47d7fbd9b6fc8afa8460d340e4ae0e6f5419ebbd7539a10 manager: conda name: brotli-bin optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/brotli-bin-1.0.9-h166bdaf_8.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/brotli-bin-1.0.9-h166bdaf_9.conda version: 1.0.9 - category: main dependencies: - gcc_impl_linux-64: '>=12.2.0,<12.2.1.0a0' + gcc_impl_linux-64: '>=12.3.0,<12.3.1.0a0' hash: - md5: 8b6a817ae6f518315cd82a8e826077e8 - sha256: d5230896809664dec267b3f06b50586de5d7cda22a914b82dc5ab136251d94fd + md5: 203fbb799caffdf242ccef5f9879d3a1 + sha256: b9db23cd4fd2df43c06734b3cdb7491e03472679282a058bca7148455704b6a4 manager: conda name: conda-gcc-specs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/conda-gcc-specs-12.2.0-he6d4335_19.tar.bz2 - version: 12.2.0 + url: https://conda.anaconda.org/conda-forge/linux-64/conda-gcc-specs-12.3.0-h83fac38_0.conda + version: 12.3.0 - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -1666,16 +1684,16 @@ package: version: 2.12.1 - category: main dependencies: - gcc_impl_linux-64: 12.2.0.* + gcc_impl_linux-64: 12.3.0.* hash: - md5: ec93d13e0fe8514f65842120dbae1b16 - sha256: 5478f5b7672b6c2d5b644aaa9fe18fbb1468ca6ea9cea1b0f0a2254459438e24 + md5: cb7c7892032ecf45fcad76d67b6a3e9b + sha256: 19d68909b1016ce07f6d3056e32d23dbade083111ac2110ab1782c1309164234 manager: conda name: gcc optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gcc-12.2.0-h26027b1_13.conda - version: 12.2.0 + url: https://conda.anaconda.org/conda-forge/linux-64/gcc-12.3.0-h8d2909c_1.conda + version: 12.3.0 - category: main dependencies: libgcc-ng: '>=12' @@ -1695,18 +1713,18 @@ package: version: 3.7.8 - category: main dependencies: - gcc_impl_linux-64: 12.2.0 hcc96c02_19 - libstdcxx-devel_linux-64: 12.2.0 h3b97bd3_19 + gcc_impl_linux-64: 12.3.0 he2b93b0_0 + libstdcxx-devel_linux-64: 12.3.0 h8bca6fd_0 sysroot_linux-64: '' hash: - md5: 698aae34e4f5e0ea8eac0d529c8f20b6 - sha256: eaca73bdeabe7d862f41e88be18788d00bd2135bc6003bbe7423e96c4275b944 + md5: 3f00aa0a8f8d3924890fecae937cc6bd + sha256: 87c7ec85f76aa065c2c991acd7bbf86d25b4724bc283f793400c14f5d5e39aa0 manager: conda name: gxx_impl_linux-64 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gxx_impl_linux-64-12.2.0-hcc96c02_19.tar.bz2 - version: 12.2.0 + url: https://conda.anaconda.org/conda-forge/linux-64/gxx_impl_linux-64-12.3.0-he2b93b0_0.conda + version: 12.3.0 - category: main dependencies: keyutils: '>=1.6.1,<2.0a0' @@ -1745,15 +1763,15 @@ package: version: 3.5.2 - category: main dependencies: - libblas: 3.9.0 16_linux64_openblas + libblas: 3.9.0 17_linux64_openblas hash: - md5: 20bae26d0a1db73f758fc3754cab4719 - sha256: e4ceab90a49cb3ac1af20177016dc92066aa278eded19646bb928d261b98367f + md5: 7ef0969b00fe3d6eef56a8151d3afb29 + sha256: 535bc0a6bc7641090b1bdd00a001bb6c4ac43bce2a11f238bc6676252f53eb3f manager: conda name: libcblas optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libcblas-3.9.0-16_linux64_openblas.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/libcblas-3.9.0-17_linux64_openblas.conda version: 3.9.0 - category: main dependencies: @@ -1765,25 +1783,25 @@ package: libzlib: '>=1.2.13,<1.3.0a0' pcre2: '>=10.40,<10.41.0a0' hash: - md5: a64f11b244b2c112cd3fa1cbe9493999 - sha256: 6a34c6b123f06fcee7e28e981ec0daad09bce35616ad8e9e61ef84be7fad4d92 + md5: c6f951789c888f7bbd2dd6858eab69de + sha256: e909b5e648d1ace172aac2ddf9d755f72429b134155a9b07156acb58a77ceee1 manager: conda name: libglib optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libglib-2.76.3-hebfc3b9_0.conda - version: 2.76.3 + url: https://conda.anaconda.org/conda-forge/linux-64/libglib-2.76.4-hebfc3b9_0.conda + version: 2.76.4 - category: main dependencies: - libblas: 3.9.0 16_linux64_openblas + libblas: 3.9.0 17_linux64_openblas hash: - md5: 955d993f41f9354bf753d29864ea20ad - sha256: f5f30b8049dfa368599e5a08a4f35cb1966af0abc539d1fd1f50d93db76a74e6 + md5: a2103882c46492e26500fcb56c03de8b + sha256: 45128394d2f4d4caf949c1b02bff1cace3ef2e33762dbe8f0edec7701a16aaa9 manager: conda name: liblapack optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/liblapack-3.9.0-16_linux64_openblas.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/liblapack-3.9.0-17_linux64_openblas.conda version: 3.9.0 - category: main dependencies: @@ -1829,31 +1847,31 @@ package: xz: '>=5.2.6,<6.0a0' zstd: '>=1.5.2,<1.6.0a0' hash: - md5: 4e5ee4b062c21519efbee7e2ae608748 - sha256: caacb23e1b95fbdd8115be69228f9c82068ed87bf57f055027e31d093ae6a1a2 + md5: 8ad377fb60abab446a9f02c62b3c2190 + sha256: 920943ad46869938bd070ccd4c0117594e07538bc6b27b75462594c67b6f215d manager: conda name: libtiff optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libtiff-4.5.0-ha587672_6.conda - version: 4.5.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libtiff-4.5.1-h8b53f26_0.conda + version: 4.5.1 - category: main dependencies: libgcc-ng: '>=12' - libprotobuf: '>=4.23.2,<4.23.3.0a0' + libprotobuf: '>=4.23.3,<4.23.4.0a0' libstdcxx-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' - ncurses: '>=6.3,<7.0a0' - openssl: '>=3.1.0,<4.0a0' + ncurses: '>=6.4,<7.0a0' + openssl: '>=3.1.1,<4.0a0' perl: '>=5.32.1,<5.33.0a0 *_perl5' hash: - md5: 2cf0c4f7a0a46c75e27735d16fab1501 - sha256: 412157ab852270658e1b96e6f66e00f8ca7039ea8d4ae24090b1d3f726fadfac + md5: 434a2df8dbd192cb511290763a4f93d8 + sha256: b0424b21c5d1790c04e96a7d62e10326fa3c8b0c263ad8cb4eda707b94317f98 manager: conda name: mosh optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/mosh-1.4.0-pl5321h4605741_1.conda + url: https://conda.anaconda.org/conda-forge/linux-64/mosh-1.4.0-pl5321hc529e37_2.conda version: 1.4.0 - category: main dependencies: @@ -1876,24 +1894,24 @@ package: libffi: '>=3.4,<4.0a0' libgcc-ng: '>=12' libnsl: '>=2.0.0,<2.1.0a0' - libsqlite: '>=3.41.2,<4.0a0' + libsqlite: '>=3.42.0,<4.0a0' libuuid: '>=2.38.1,<3.0a0' libzlib: '>=1.2.13,<1.3.0a0' - ncurses: '>=6.3,<7.0a0' - openssl: '>=3.1.0,<4.0a0' + ncurses: '>=6.4,<7.0a0' + openssl: '>=3.1.1,<4.0a0' readline: '>=8.2,<9.0a0' tk: '>=8.6.12,<8.7.0a0' tzdata: '' xz: '>=5.2.6,<6.0a0' hash: - md5: 7439c9d24378a82b73a7a53868dacdf1 - sha256: 6682c75caf3456796fb76313a25475738d85729b43f8c0e904407c0ed8362ede + md5: eb6f1df105f37daedd6dca78523baa75 + sha256: 05e2a7ce916d259f11979634f770f31027d0a5d18463b094e64a30500f900699 manager: conda name: python optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/python-3.10.11-he550d4f_0_cpython.conda - version: 3.10.11 + url: https://conda.anaconda.org/conda-forge/linux-64/python-3.10.12-hd12c33a_0_cpython.conda + version: 3.10.12 - category: main dependencies: libgcc-ng: '>=12' @@ -1953,14 +1971,14 @@ package: xorg-xextproto: '>=7.3.0,<8.0a0' xorg-xproto: '' hash: - md5: 52d09ea80a42c0466214609ef0a2d62d - sha256: 26e5c72def9f1b191afea84aa2d09622d34b2f547a446eac201ecf894521e5ee + md5: 7590b76c3d11d21caa44f3fc38ac584a + sha256: 3360f81f7687179959a6bf1c762938240172e8bb3aef957e0a14fb12a0b7c105 manager: conda name: xorg-libx11 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libx11-1.8.4-h8ee46fc_1.conda - version: 1.8.4 + url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libx11-1.8.6-h8ee46fc_0.conda + version: 1.8.6 - category: main dependencies: python: '>=3.6' @@ -1987,16 +2005,16 @@ package: version: 1.4.4 - category: main dependencies: - python: '>=3.7' + python: '>=3.8' hash: - md5: 0b3460f5bf4ae27dfd72fdcccc9667a9 - sha256: 18aad01518cb08e4eff18e507e14ebf6c522d89ef53ca267c48080933c4435f7 + md5: 964bace0c38ce4733851a2a29679e3f9 + sha256: 1fe9b55d3daeb26ac404ec51f106ce8792d7d6548810ca87600cd9b9e9cfbd6e manager: conda name: argcomplete optional: false platform: linux-64 - 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category: main dependencies: python: '>=3.10,<3.11.0a0' @@ -2452,16 +2482,16 @@ package: - category: main dependencies: libgcc-ng: '>=12' - python: '>=3.9,<3.10.0a0' - python_abi: 3.9.* *_cp39 + python: '>=3.10,<3.11.0a0' + python_abi: 3.10.* *_cp310 hash: - md5: a0238daacd28c07735c6bc75aedf2014 - sha256: bbae929b429f39a10432e86d87bf02864e6640287245de71edeac6b3c29b0ff7 + md5: 8664f43451412071a7111211fe7e38f2 + sha256: a26e8c55b8d1b17e784c6e2ffa75ed4dec4a335c7df17f183dcc9c5149d6cd70 manager: conda name: lazy-object-proxy optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/lazy-object-proxy-1.9.0-py39h72bdee0_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/lazy-object-proxy-1.9.0-py310h1fa729e_0.conda version: 1.9.0 - category: main dependencies: @@ -2558,14 +2588,14 @@ package: gnutls: '>=3.7.8,<3.8.0a0' libgcc-ng: '>=12' hash: - md5: a946cb6b36807a772748b55f59089a08 - sha256: 33ddfa3d91816ee44df405424ee2fedf5df5c02a1ffa1819aa4c956eedae4533 + md5: 20e3667699ceaae97d6ba110a098e8f8 + sha256: 8530794bb59332eefea6af1e7e3e7289a5fe40d2c4d265357af72b67ff6ee38e manager: conda name: libmicrohttpd optional: false platform: linux-64 - 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category: main dependencies: python: '' @@ -2613,26 +2643,38 @@ package: python: '>=3.10,<3.11.0a0' python_abi: 3.10.* *_cp310 hash: - md5: a1f0db6709778b77b5903541eeac4032 - sha256: f62b2aeafe968472b20b6935fa7b2290d27ac38b65d98b2708c7cf0b689f9f19 + md5: 5597d9f9778af6883ae64f0e7d39416c + sha256: 91509d88d073f5baf30866219cee9c8ecef839fa9874fee600e46531c2822621 manager: conda name: markupsafe optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/markupsafe-2.1.2-py310h1fa729e_0.conda - version: 2.1.2 + url: https://conda.anaconda.org/conda-forge/linux-64/markupsafe-2.1.3-py310h2372a71_0.conda + version: 2.1.3 - category: main dependencies: - python: '>=3.6' + python: '>=3.8' hash: - md5: 1698a717f83cfecf644a877c174c84bd - sha256: 3ee8cbbe4004c56b695a5e734b7dc4d59dacbfefc193ee42c82238b1cf888e08 + md5: 0c99f4c67b2744030d73c074cdaf2ed4 + sha256: 06d9244eb2cac341abaf1e320065761d125ffeb1dff29af59b8f2d72092cbc23 manager: conda name: more-itertools optional: false platform: linux-64 - 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category: main dependencies: __unix: '' - conda: '>=4.6,<23.1.0' + conda: '>=4.6' conda-standalone: '' pillow: '>=3.1' python: '>=3.7' - ruamel_yaml: '>=0.11.14,<0.16' + ruamel.yaml: '>=0.11.14,<0.18' hash: - md5: 531dd21a6980012d3f5c01f9e5335c5b - sha256: 311cd96ecabd6557daa8aecaef858fb053acf4cda195a1d34a9a28c998807596 + md5: 6935bda357fb4052a82a8c3ce17b176a + sha256: 7cdc83ef761fa4e8dff316e49f7b2c839a5a87cd3516762de2a36c4082af5109 manager: conda name: constructor optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/constructor-3.4.3-pyhe4f9e05_0.conda - version: 3.4.3 + url: https://conda.anaconda.org/conda-forge/noarch/constructor-3.4.4-pyh55f8243_0.conda + version: 3.4.4 - category: main dependencies: msal: '>=0.4.1,<2.0' @@ -5448,19 +5556,20 @@ package: version: '4.1' - category: main dependencies: - boto3: ~=1.5 - jsonschema: ~=3.2 - python: '>=3.6' - six: ~=1.15 + boto3: '>=1.19.5,<2' + jsonschema: '>=3.2,<5' + pydantic: ~=1.10.2 + python: '>=3.7' + typing_extensions: '>=4.4.0,<5' hash: - md5: 6a8ad721f4edea85a40070c78f379dd4 - sha256: d9b2ff5fdf1e8de7cf80f2a14a7cb76c65c0bae18a2fe51700e6ed3c71fdb5b5 + md5: e8626fbe4927c8ff91046c69a53e85b1 + sha256: 8ec742faf22a0480b4e527e404d38dd2da56ac9e6212b8b5d0c5c9088548b11a manager: conda name: aws-sam-translator optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/aws-sam-translator-1.55.0-pyhd8ed1ab_0.conda - version: 1.55.0 + url: https://conda.anaconda.org/conda-forge/noarch/aws-sam-translator-1.72.0-pyhd8ed1ab_0.conda + version: 1.72.0 - category: main dependencies: azure-core: '>=1.11.0,<2.0.0' @@ -5530,14 +5639,14 @@ package: python: '' typing_extensions: '' hash: - md5: 1cc6dd0f40481c8a20eaa91a76f48ce5 - sha256: c0c0c81cfaf11a662d331d934d7a8eca12adbf12fa89a1fd60b514318c87c6c8 + md5: e17411f5fd284effa5c22b3e5a057b42 + sha256: 9d66120f62477e3b2d37c44cf8a1990a9aa52dac8488f9aec4f2623df4afa85d manager: conda name: boto3-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.145-pyhd8ed1ab_0.conda - version: 1.26.145 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.28.15.post1-pyhd8ed1ab_0.conda + version: 1.28.15.post1 - category: main dependencies: cachecontrol-with-filecache: '>=0.12.9' @@ -5578,28 +5687,28 @@ package: python: '>=3.6' typing-extensions: '' hash: - md5: adb30ee4ef9f506b62f732c8a78d250b - sha256: 281ba68f92f05626bf37df32156abbf62e6ed963ab40b2205277a066391cc06f + md5: 7783f63b4d3b1755e08c268efc4340ff + sha256: 92ae281387cead901e33d7a6aac067d445c80c7b8e97216b6fa99d11a21d841b manager: conda name: mypy-boto3-s3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.26.127-pyhd8ed1ab_0.conda - version: 1.26.127 + url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.28.15.post1-pyhd8ed1ab_0.conda + version: 1.28.15.post1 - category: main dependencies: boto3: '' python: '>=3.6' typing-extensions: '' hash: - md5: 2f58c5525f108a1525553e081c90f815 - sha256: 66d980a4aa02be974410c64d0631ea54d26e538f49300ac5e3b46d44a4acec78 + md5: 84d0f7bec4027ed80ec4fd17f32e359a + sha256: fbf43754b34157a131344e8ac077a366f88e679bc46617c2c9888a895403af53 manager: conda name: mypy_boto3_ec2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.136-pyhd8ed1ab_0.conda - version: 1.26.136 + url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.28.15.post1-pyhd8ed1ab_0.conda + version: 1.28.15.post1 - category: main dependencies: boto3: '' @@ -5619,36 +5728,38 @@ package: docutils: <0.19 python: '>=2.7,!=3.0.*,!=3.1.*,!=3.2.*,!=3.3.*,!=3.4.*,!=3.5.*' sphinx: '>=1.6,<7' - sphinxcontrib-jquery: '>=2.0.0,!=3.0.0' + sphinxcontrib-jquery: '>=4,<5' hash: - md5: dd1ec3c6beac662d7bf9c996975f637f - sha256: 818659eb58b74da694e7ff6ecb907d417ae0de4db8231c42f0b0ba75f56ef3f4 + md5: 5ef6aaf2cfb3b656cdadb431daed6a9f + sha256: 129cab0a4cddd57fa58930c306ca8363c8ac2c40bd40b784210603b17abb5639 manager: conda name: sphinx_rtd_theme optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/sphinx_rtd_theme-1.2.1-pyha770c72_0.conda - version: 1.2.1 + url: https://conda.anaconda.org/conda-forge/noarch/sphinx_rtd_theme-1.2.2-pyha770c72_0.conda + version: 1.2.2 - category: main dependencies: - aws-sam-translator: '>=1.55.0' + aws-sam-translator: '>=1.70.0' jschema-to-python: ~=1.2.3 jsonpatch: '' - jsonschema: '>=3.0,<5' + jsonschema: <4.18,>=3.0 junit-xml: ~=1.9 - networkx: ~=2.4 + networkx: ~=2.4,<4 python: '>=3.7' pyyaml: '>5.4' + regex: '' sarif-om: ~=1.0.4 + sympy: '>=1.0.0' hash: - md5: 97bf916949bb4eb9f69c77d365a4da72 - sha256: 7d8c32e83b839abbb4c2a6b476b2a4a60f03394ac6156740f81abba64dbcf756 + md5: ee8a8cc440ae8b2df83b046bd981b414 + sha256: 90c439cedcdf9ce5ed4f3d368cf1db7ce4ba12227c38d216c4e8f7ab25999db4 manager: conda name: cfn-lint optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.75.1-pyhd8ed1ab_0.conda - version: 0.75.1 + url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.79.5-pyhd8ed1ab_0.conda + version: 0.79.5 - category: main dependencies: aws-xray-sdk: '!=0.96,>=0.93' @@ -5678,14 +5789,14 @@ package: werkzeug: '>=0.5,!=2.2.0,!=2.2.1' xmltodict: '' hash: - md5: 7f8865d0f6df238a407cab06d884c211 - sha256: c51cc65dac1b0b1f5139860c07030b9465417cebcb8529ffa97fcd8615aba606 + md5: f5f07ac7435c82ce5daa20aa2e2ed522 + sha256: 329e2db3705ee0f29b821a9a06eb80564490898a76a8882ec048fc4eaac64d96 manager: conda name: moto optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.10-pyhd8ed1ab_0.conda - version: 4.1.10 + url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.13-pyhd8ed1ab_0.conda + version: 4.1.13 - category: main dependencies: {} hash: diff --git a/conda-reqs/firesim.yaml b/conda-reqs/firesim.yaml index b57bbd15..79a386eb 100644 --- a/conda-reqs/firesim.yaml +++ b/conda-reqs/firesim.yaml @@ -23,8 +23,8 @@ dependencies: # bundle FireSim driver with deps into installer shell-script - constructor - - gcc - - gxx + - gcc<13 + - gxx<13 - sysroot_linux-64=2.17 # needed to match pre-built CI XRT glibc version - conda-gcc-specs - binutils @@ -88,6 +88,7 @@ dependencies: - elfutils - libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock - conda-lock=1.4 + - autoconf # clang-format for driver coding style enforcement. - clang-format diff --git a/deploy/buildtools/bitbuilder.py b/deploy/buildtools/bitbuilder.py index ef58980f..f742ae51 100644 --- a/deploy/buildtools/bitbuilder.py +++ b/deploy/buildtools/bitbuilder.py @@ -685,6 +685,7 @@ class XilinxAlveoBitBuilder(BitBuilder): local_cl_dir = f"{local_results_dir}/{fpga_build_postfix}" bit_path = f"{local_cl_dir}/vivado_proj/firesim.bit" mcs_path = f"{local_cl_dir}/vivado_proj/firesim.mcs" + mcs_secondary_path = f"{local_cl_dir}/vivado_proj/firesim_secondary.mcs" tar_staging_path = f"{local_cl_dir}/{self.build_config.PLATFORM}" tar_name = "firesim.tar.gz" @@ -694,8 +695,9 @@ class XilinxAlveoBitBuilder(BitBuilder): # store bitfile (and mcs if it exists) local(f"cp {bit_path} {tar_staging_path}") - if self.build_config.PLATFORM != "xilinx_vcu118": - local(f"cp {mcs_path} {tar_staging_path}") + local(f"cp {mcs_path} {tar_staging_path}") + if self.build_config.PLATFORM == "xilinx_vcu118": + local(f"cp {mcs_secondary_path} {tar_staging_path}") # store metadata string local(f"""echo '{self.get_metadata_string()}' >> {tar_staging_path}/metadata""") @@ -848,4 +850,3 @@ class RHSResearchNitefuryIIBitBuilder(XilinxAlveoBitBuilder): rootLogger.debug(rsync_cap.stderr) return f"{dest_alveo_dir}/{fpga_build_postfix}" - diff --git a/deploy/sample-backup-configs/sample_config_hwdb.yaml b/deploy/sample-backup-configs/sample_config_hwdb.yaml index ec3450db..7b550d0d 100644 --- a/deploy/sample-backup-configs/sample_config_hwdb.yaml +++ b/deploy/sample-backup-configs/sample_config_hwdb.yaml @@ -11,12 +11,12 @@ # DOCREF START: Example HWDB Entry firesim_boom_singlecore_nic_l2_llc4mb_ddr3: - agfi: agfi-00e99bd64c0643ac9 + agfi: agfi-03332c26b0bfef9cf deploy_quintuplet_override: null custom_runtime_config: null # DOCREF END: Example HWDB Entry firesim_boom_singlecore_no_nic_l2_llc4mb_ddr3: - agfi: agfi-0d475d004a5929ce1 + agfi: agfi-0b01cb001eb3db84b deploy_quintuplet_override: null custom_runtime_config: null firesim_gemmini_printf_rocket_singlecore_no_nic: @@ -28,11 +28,11 @@ firesim_gemmini_rocket_singlecore_no_nic: deploy_quintuplet_override: null custom_runtime_config: null firesim_rocket_quadcore_nic_l2_llc4mb_ddr3: - agfi: agfi-03c40fa49ed5c84e8 + agfi: agfi-0d37db88b8d6a9ea9 deploy_quintuplet_override: null custom_runtime_config: null firesim_rocket_quadcore_no_nic_l2_llc4mb_ddr3: - agfi: agfi-0e55df16a9ca937aa + agfi: agfi-05ad3a0d05b659fe8 deploy_quintuplet_override: null custom_runtime_config: null firesim_rocket_singlecore_no_nic_l2_lbp: @@ -52,11 +52,11 @@ firesim_rocket_singlecore_sha3_no_nic_l2_llc4mb_ddr3_printf: deploy_quintuplet_override: null custom_runtime_config: null firesim_supernode_rocket_singlecore_nic_l2_lbp: - agfi: agfi-049822fd73bc2fca1 + agfi: agfi-0541dd890b2b59bd5 deploy_quintuplet_override: null custom_runtime_config: null vitis_firesim_rocket_singlecore_no_nic: - bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/72d12f12eb24fa99e5943723990c1d44df054006/vitis/vitis_firesim_rocket_singlecore_no_nic.tar.gz + bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/f17bff0afb96d278c3cd199a72d9317b1bebbb2a/vitis/vitis_firesim_rocket_singlecore_no_nic.tar.gz deploy_quintuplet_override: null custom_runtime_config: null vitis_firesim_gemmini_rocket_singlecore_no_nic: @@ -64,26 +64,26 @@ vitis_firesim_gemmini_rocket_singlecore_no_nic: deploy_quintuplet_override: null custom_runtime_config: null alveo_u250_firesim_rocket_singlecore_no_nic: - bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/1dc6be48bfe043bbc47e24660c1ef5076a22b7e4/xilinx_alveo_u250/alveo_u250_firesim_rocket_singlecore_no_nic.tar.gz + bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/9543b082437e3ec2c3ecc863da4e06a19597e5e6/xilinx_alveo_u250/alveo_u250_firesim_rocket_singlecore_no_nic.tar.gz deploy_quintuplet_override: null custom_runtime_config: null alveo_u250_firesim_gemmini_rocket_singlecore_no_nic: - bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/9de6c6cd854ff613114b04a2c67d7558e55d456c/xilinx_alveo_u250/alveo_u250_firesim_gemmini_rocket_singlecore_no_nic.tar.gz + bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/933a8726645fd7241f019463df86f3d117a7d714/xilinx_alveo_u250/alveo_u250_firesim_gemmini_rocket_singlecore_no_nic.tar.gz deploy_quintuplet_override: null custom_runtime_config: null alveo_u200_firesim_rocket_singlecore_no_nic: - bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/0abb07d46eced6b54e07026533f85bdc73f5a15e/xilinx_alveo_u200/alveo_u200_firesim_rocket_singlecore_no_nic.tar.gz + bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/0d91a839113ab048abfed7e79fe2b0d1097f2807/xilinx_alveo_u200/alveo_u200_firesim_rocket_singlecore_no_nic.tar.gz deploy_quintuplet_override: null custom_runtime_config: null alveo_u280_firesim_rocket_singlecore_no_nic: - bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/f445dd689c74d9e9c8e5fdba19e299488f9446ce/xilinx_alveo_u280/alveo_u280_firesim_rocket_singlecore_no_nic.tar.gz + bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/a8b9ffaeb4d243292c04eb13857a7daa8ac6d897/xilinx_alveo_u280/alveo_u280_firesim_rocket_singlecore_no_nic.tar.gz deploy_quintuplet_override: null custom_runtime_config: null xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic: - bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/df66683984628552f25acba52e5247ed78321994/xilinx_vcu118/xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic.tar.gz + bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/48934d5a7b6b5869b446378656cf61824961471e/xilinx_vcu118/xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic.tar.gz deploy_quintuplet_override: null custom_runtime_config: null nitefury_firesim_rocket_singlecore_no_nic: - bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/b06e34569c2e4b350f8adeb96168244f2d43422b/rhsresearch_nitefury_ii/nitefury_firesim_rocket_singlecore_no_nic.tar.gz + bitstream_tar: https://raw.githubusercontent.com/firesim/firesim-public-bitstreams/f228aa51f95c3a7022444516051fd2fe346cc48d/rhsresearch_nitefury_ii/nitefury_firesim_rocket_singlecore_no_nic.tar.gz deploy_quintuplet_override: null - custom_runtime_config: null + custom_runtime_config: null \ No newline at end of file diff --git a/deploy/workloads/ci/hello-world-localhost-vcs-metasim.yaml b/deploy/workloads/ci/hello-world-localhost-vcs-metasim.yaml index 918cbb17..4f3baedd 100644 --- a/deploy/workloads/ci/hello-world-localhost-vcs-metasim.yaml +++ b/deploy/workloads/ci/hello-world-localhost-vcs-metasim.yaml @@ -3,7 +3,7 @@ run_farm: recipe_arg_overrides: run_farm_tag: helloworldlocalhost default_platform: VitisInstanceDeployManager - default_simulation_dir: /scratch/buildbot + default_simulation_dir: /scratch/buildbot/RUN_DIR run_farm_hosts_to_use: - localhost: four_metasims_spec diff --git a/deploy/workloads/ci/hello-world-localhost-verilator-metasim.yaml b/deploy/workloads/ci/hello-world-localhost-verilator-metasim.yaml index 9ea57a92..dafe16f2 100644 --- a/deploy/workloads/ci/hello-world-localhost-verilator-metasim.yaml +++ b/deploy/workloads/ci/hello-world-localhost-verilator-metasim.yaml @@ -3,7 +3,7 @@ run_farm: recipe_arg_overrides: run_farm_tag: helloworldlocalhost default_platform: EC2InstanceDeployManager - default_simulation_dir: /home/centos + default_simulation_dir: /home/centos/RUN_DIR run_farm_hosts_to_use: - localhost: four_metasims_spec diff --git a/deploy/workloads/ci/vitis/config_runtime.yaml b/deploy/workloads/ci/vitis/config_runtime.yaml index 2b0ec38c..b8c8c72e 100644 --- a/deploy/workloads/ci/vitis/config_runtime.yaml +++ b/deploy/workloads/ci/vitis/config_runtime.yaml @@ -2,14 +2,9 @@ run_farm: base_recipe: run-farm-recipes/externally_provisioned.yaml recipe_arg_overrides: default_platform: VitisInstanceDeployManager - default_simulation_dir: /scratch/buildbot + default_simulation_dir: /scratch/buildbot/RUN_DIR run_farm_hosts_to_use: - - localhost: four_fpgas_spec - run_farm_host_specs: - - four_fpgas_spec: - num_fpgas: 4 - num_metasims: 0 - use_for_switch_only: false + - harp: one_fpga_spec metasimulation: metasimulation_enabled: false diff --git a/docs/Advanced-Usage/Manager/Manager-Configuration-Files.rst b/docs/Advanced-Usage/Manager/Manager-Configuration-Files.rst index aa14474b..51b6880f 100644 --- a/docs/Advanced-Usage/Manager/Manager-Configuration-Files.rst +++ b/docs/Advanced-Usage/Manager/Manager-Configuration-Files.rst @@ -413,7 +413,7 @@ Specifies the host FPGA frequency for a bitstream build. Specifies a pre-canned set of strategies and directives to pass to the bitstream build. Note, these are implemented differently on different host -platforms, but try to optimize for the same things. Strategies supported across both Vitis, Xilinx Alveo U250/U280, and EC2 F1 include: +platforms, but try to optimize for the same things. Strategies supported across both Vitis, Xilinx Alveo U200/U250/U280, and EC2 F1 include: - ``TIMING``: Optimize for improved fmax. - ``AREA``: Optimize for reduced resource utilization. @@ -748,7 +748,7 @@ simulations across all run farm hosts. For example, this class manages how to flash FPGAs with bitstreams, how to copy back results, and how to check if a simulation is running. By default, deploy platform classes can be found in :gh-file-ref:`deploy/runtools/run_farm_deploy_managers.py`. However, you can specify your own custom run farm classes by adding your python file to the ``PYTHONPATH``. -There are default deploy managers / platforms that correspond to AWS EC2 F1 FPGAs, Vitis FPGAs, Xilinx Alveo U250/U280 FPGAs, Xilinx VCU118 FPGAs, and RHS Research Nitefury II FPGAs: ``EC2InstanceDeployManager``, ``VitisInstanceDeployManager``, ``Xilinx{AlveoU250,AlveoU280,VCU118}InstanceDeployManager``, and ``RHSResearchNitefuryIIInstanceDeployManager`` respectively. +There are default deploy managers / platforms that correspond to AWS EC2 F1 FPGAs, Vitis FPGAs, Xilinx Alveo U200/U250/U280 FPGAs, Xilinx VCU118 FPGAs, and RHS Research Nitefury II FPGAs: ``EC2InstanceDeployManager``, ``VitisInstanceDeployManager``, ``Xilinx{AlveoU200,AlveoU250,AlveoU280,VCU118}InstanceDeployManager``, and ``RHSResearchNitefuryIIInstanceDeployManager`` respectively. For example, to use the ``EC2InstanceDeployManager`` deploy platform class, you would write ``default_platform: EC2InstanceDeployManager``. ``default_simulation_dir`` @@ -948,6 +948,11 @@ Here is an example of this configuration file: .. literalinclude:: /../deploy/bit-builder-recipes/vitis.yaml :language: yaml +``xilinx_alveo_u200.yaml`` bit builder recipe +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This bit builder recipe configures a build farm host to build an Xilinx Alveo U200 bitstream, packaged into a ``bitstream_tar``. + ``xilinx_alveo_u250.yaml`` bit builder recipe ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -967,4 +972,3 @@ This bit builder recipe configures a build farm host to build an Xilinx VCU118 b ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This bit builder recipe configures a build farm host to build an RHS Research Nitefury II bitstream, packaged into a ``bitstream_tar``. - diff --git a/docs/Advanced-Usage/Manager/Manager-Tasks.rst b/docs/Advanced-Usage/Manager/Manager-Tasks.rst index b30d0508..dd165c32 100644 --- a/docs/Advanced-Usage/Manager/Manager-Tasks.rst +++ b/docs/Advanced-Usage/Manager/Manager-Tasks.rst @@ -25,7 +25,7 @@ Then, do platform-specific init steps for the given ``--platform``. .. tab:: All other platforms - This includes platforms such as: ``xilinx_alveo_u250``, ``xilinx_alveo_u280``, ``xilinx_vcu118``, and ``rhsresearch_nitefury_ii``. + This includes platforms such as: ``xilinx_alveo_u200``, ``xilinx_alveo_u250``, ``xilinx_alveo_u280``, ``xilinx_vcu118``, and ``rhsresearch_nitefury_ii``. * Setup the ``config_runtime.yaml`` and ``config_build.yaml`` files with externally provisioned run/build farm arguments. @@ -271,7 +271,7 @@ RUN FARM WITHOUT PROMPTING FOR CONFIRMATION: firesim terminaterunfarm --forceterminate -The ``--terminatesome=INSTANCE_TYPE:COUNT`` flag additionally allows you to +The ``--terminatesome=INSTANCE_TYPE:COUNT`` flag additionally allows you to terminate only some (``COUNT``) of the instances of a particular type (``INSTANCE_TYPE``) in a particular Run Farm. @@ -426,4 +426,3 @@ used to run simulations for each FPGA attached to the machine. If you ever change the physical layout of a Run Farm Machine in your Run Farm (e.g., which PCIe slot the FPGAs are attached to), you will need to re-run this command. - diff --git a/docs/FireSim-Basics.rst b/docs/FireSim-Basics.rst index a3a2ac7c..6e8e5178 100644 --- a/docs/FireSim-Basics.rst +++ b/docs/FireSim-Basics.rst @@ -6,9 +6,9 @@ FireSim Basics FireSim is an open-source FPGA-accelerated full-system hardware simulation platform that makes it easy to validate, profile, and debug RTL hardware implementations -at 10s to 100s of MHz. FireSim simplifies co-simulating -ASIC RTL with cycle-accurate hardware and software models for other system components (e.g. I/Os). FireSim can productively -scale from individual SoC simulations hosted on on-prem FPGAs (e.g., a single Xilinx Alveo board attached to a desktop) +at 10s to 100s of MHz. FireSim simplifies co-simulating +ASIC RTL with cycle-accurate hardware and software models for other system components (e.g. I/Os). FireSim can productively +scale from individual SoC simulations hosted on on-prem FPGAs (e.g., a single Xilinx Alveo board attached to a desktop) to massive datacenter-scale simulations harnessing hundreds of cloud FPGAs (e.g., on Amazon EC2 F1). FireSim users across academia and industry (at 20+ institutions) have published @@ -84,26 +84,29 @@ Choose your platform to get started FireSim supports many types of FPGAs and FPGA platforms! Click one of the following links to work through the getting started guide for your particular platform. * :doc:`/Getting-Started-Guides/AWS-EC2-F1-Getting-Started/index` - + + * Status: ✅ All FireSim Features Supported. + +* :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U200-FPGAs` + * Status: ✅ All FireSim Features Supported. * :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs` - + * Status: ✅ All FireSim Features Supported. * :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U280-FPGAs` - + * Status: ✅ All FireSim Features Supported. * :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-VCU118-FPGAs` - + * Status: ✅ All FireSim Features Supported. * :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/RHS-Research-Nitefury-II-FPGAs` - + * Status: ✅ All FireSim Features Supported. * :doc:`Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Vitis-FPGAs` - - * Status: ⚠️ DMA-based Bridges Not Supported. The Vitis-based U250 flow is **not recommended** unless you have specific constraints that require using Vitis. Notably, the Vitis-based flow does not support DMA-based FireSim bridges (e.g., TracerV, Synthesizable Printfs, etc.), while the XDMA-based flows support all FireSim features, as shown above. If you're unsure, use the XDMA-based U250 flow instead: :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs`. + * Status: ⚠️ DMA-based Bridges Not Supported. The Vitis-based U250 flow is **not recommended** unless you have specific constraints that require using Vitis. Notably, the Vitis-based flow does not support DMA-based FireSim bridges (e.g., TracerV, Synthesizable Printfs, etc.), while the XDMA-based flows support all FireSim features, as shown above. If you're unsure, use the XDMA-based U250 flow instead: :doc:`/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs`. diff --git a/docs/Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/Configuring-Required-Infrastructure-in-Your-AWS-Account.rst b/docs/Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/Configuring-Required-Infrastructure-in-Your-AWS-Account.rst index f0e653e9..d7814011 100644 --- a/docs/Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/Configuring-Required-Infrastructure-in-Your-AWS-Account.rst +++ b/docs/Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/Configuring-Required-Infrastructure-in-Your-AWS-Account.rst @@ -126,6 +126,7 @@ output format to ``json``. You will need to generate an AWS access key in the "S Again on the ``t2.nano`` instance, do the following: .. code-block:: bash + :substitutions: sudo yum install -y python3-pip sudo python3 -m pip install boto3 diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Building-a-FireSim-Bitstream/Xilinx-Alveo-U200.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Building-a-FireSim-Bitstream/Xilinx-Alveo-U200.rst new file mode 100644 index 00000000..49810b0c --- /dev/null +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Building-a-FireSim-Bitstream/Xilinx-Alveo-U200.rst @@ -0,0 +1,18 @@ +.. |fpga_name| replace:: Xilinx Alveo U200 +.. |hwdb_entry_name| replace:: ``alveo_u200_firesim_rocket_singlecore_no_nic`` +.. |hwdb_entry_name_non_code| replace:: alveo_u200_firesim_rocket_singlecore_no_nic +.. |builder_name| replace:: Xilinx Vivado +.. |bit_builder_path| replace:: ``bit-builder-recipes/xilinx_alveo_u200.yaml`` +.. |vivado_with_version| replace:: Vivado 2021.1 +.. |vivado_version_number_only| replace:: 2021.1 +.. |vivado_default_install_path| replace:: ``/tools/Xilinx/Vivado/2021.1`` +.. |board_package_install| replace:: Download the ``au200`` board support package directory from https://github.com/Xilinx/open-nic-shell/tree/main/board_files/Xilinx and place the directory in ``/tools/Xilinx/Vivado/2021.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/``. + +Building Your Own Hardware Designs +=================================================================== + +This section will guide you through building a |fpga_name| FPGA bitstream to run FireSim simulations. + +.. include:: Xilinx-XDMA-Build-Farm-Setup-Template.rst + +.. include:: Xilinx-All-Bitstream-Template.rst diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Building-a-FireSim-Bitstream/Xilinx-VCU118.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Building-a-FireSim-Bitstream/Xilinx-VCU118.rst index 23f64376..5f30d5a1 100644 --- a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Building-a-FireSim-Bitstream/Xilinx-VCU118.rst +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Building-a-FireSim-Bitstream/Xilinx-VCU118.rst @@ -3,9 +3,9 @@ .. |hwdb_entry_name_non_code| replace:: xilinx_vcu118_firesim_rocket_singlecore_4GB_no_nic .. |builder_name| replace:: Xilinx Vivado .. |bit_builder_path| replace:: ``bit-builder-recipes/xilinx_vcu118.yaml`` -.. |vivado_with_version| replace:: Vivado 2019.1 -.. |vivado_version_number_only| replace:: 2019.1 -.. |vivado_default_install_path| replace:: ``/tools/Xilinx/Vivado/2019.1`` +.. |vivado_with_version| replace:: Vivado 2023.1 +.. |vivado_version_number_only| replace:: 2023.1 +.. |vivado_default_install_path| replace:: ``/tools/Xilinx/Vivado/2023.1`` .. |board_package_install| replace:: No special board support package is required for the VCU118. Move on to the next step. Building Your Own Hardware Designs diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/RHS-Research-Nitefury-II.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/RHS-Research-Nitefury-II.rst index b3423111..4052a99b 100644 --- a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/RHS-Research-Nitefury-II.rst +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/RHS-Research-Nitefury-II.rst @@ -11,6 +11,10 @@ .. |fpga_spi_part_number| replace:: ``s25fl256xxxxxx0-spi-x1_x2_x4`` .. |fpga_attach_prereq| replace:: into either an open M.2. slot on your machine or into an M.2. to Thunderbolt enclosure (then attach the enclosure to your system via a Thunderbolt cable). We have successfully used this enclosure: https://www.amazon.com/ORICO-Enclosure-Compatible-Thunderbolt-Type-C-M2V01/dp/B08R9DMFFT. Before permanently installing your Nitefury into your M.2. slot or enclosure, ensure that you have attached the ribbon cable that will be used for JTAG to the underside of the board (see step 4 below). .. |jtag_help| replace:: JTAG. For the Nitefury, this requires attaching the 14-pin JTAG adapter included with the board to the board using the included ribbon cable, then attaching a USB to JTAG adapter such as the Digilent HS2: https://digilent.com/shop/jtag-hs2-programming-cable/. +.. |extra_mcs| replace:: file from step 7. +.. |mcs_info| replace:: Inside, you will find three files; the one we are currently interested in will be called ``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the next step. +.. |dip_switch_extra| replace:: power). .. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. For the Nitefury to work, we will need to make one modification to the driver. Find the line containing ``#define XDMA_ENGINE_XFER_MAX_DESC``. Change the value on this line from ``0x800`` to ``16``. Then, build and install the driver: +.. |jtag_cable_reminder| replace:: Remember to keep the USB cable for JTAG connected at all times when running FireSim simulations (it is used to program the FPGA). .. include:: Xilinx-XDMA-Template.rst diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-Alveo-U200.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-Alveo-U200.rst new file mode 100644 index 00000000..2b612706 --- /dev/null +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-Alveo-U200.rst @@ -0,0 +1,20 @@ +.. |fpga_name| replace:: Xilinx Alveo U200 +.. _fpga_name: https://www.xilinx.com/products/boards-and-kits/alveo/u200.html +.. |fpga_power_info| replace:: For the U200, this is usually PCIe power coming directly from the system's PSU. +.. |hwdb_entry_name| replace:: ``alveo_u200_firesim_rocket_singlecore_no_nic`` +.. |platform_name| replace:: xilinx_alveo_u200 +.. |board_name| replace:: au200 +.. |tool_type| replace:: Xilinx Vivado +.. |tool_type_lab| replace:: Xilinx Vivado Lab +.. |example_var| replace:: ``XILINX_VIVADO`` +.. |deploy_manager_code| replace:: ``XilinxAlveoU200InstanceDeployManager`` +.. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4`` +.. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine. +.. |jtag_help| replace:: JTAG. +.. |extra_mcs| replace:: file from step 7. +.. |mcs_info| replace:: Inside, you will find three files; the one we are currently interested in will be called ``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the next step. +.. |dip_switch_extra| replace:: power). +.. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. Now, let's build and install it: +.. |jtag_cable_reminder| replace:: Remember to keep the USB cable for JTAG connected at all times when running FireSim simulations (it is used to program the FPGA). + +.. include:: Xilinx-XDMA-Template.rst diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-Alveo-U250.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-Alveo-U250.rst index 5e0b5461..dcd898c7 100644 --- a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-Alveo-U250.rst +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-Alveo-U250.rst @@ -10,7 +10,11 @@ .. |deploy_manager_code| replace:: ``XilinxAlveoU250InstanceDeployManager`` .. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4`` .. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine. -.. |jtag_help| replace:: JTAG. +.. |jtag_help| replace:: JTAG. +.. |extra_mcs| replace:: file from step 7. +.. |mcs_info| replace:: Inside, you will find three files; the one we are currently interested in will be called ``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the next step. +.. |dip_switch_extra| replace:: power). .. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. Now, let's build and install it: +.. |jtag_cable_reminder| replace:: Remember to keep the USB cable for JTAG connected at all times when running FireSim simulations (it is used to program the FPGA). .. include:: Xilinx-XDMA-Template.rst diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-Alveo-U280.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-Alveo-U280.rst index 673012ee..82cd916f 100644 --- a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-Alveo-U280.rst +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-Alveo-U280.rst @@ -10,7 +10,11 @@ .. |deploy_manager_code| replace:: ``XilinxAlveoU280InstanceDeployManager`` .. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4`` .. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine. -.. |jtag_help| replace:: JTAG. +.. |jtag_help| replace:: JTAG. +.. |extra_mcs| replace:: file from step 7. +.. |mcs_info| replace:: Inside, you will find three files; the one we are currently interested in will be called ``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the next step. +.. |dip_switch_extra| replace:: power). .. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. Now, let's build and install it: +.. |jtag_cable_reminder| replace:: Remember to keep the USB cable for JTAG connected at all times when running FireSim simulations (it is used to program the FPGA). .. include:: Xilinx-XDMA-Template.rst diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-VCU118.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-VCU118.rst index 10e5a035..a6fe37fc 100644 --- a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-VCU118.rst +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-VCU118.rst @@ -8,9 +8,13 @@ .. |tool_type_lab| replace:: Xilinx Vivado Lab .. |example_var| replace:: ``XILINX_VIVADO`` .. |deploy_manager_code| replace:: ``XilinxVCU118InstanceDeployManager`` -.. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4`` -.. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine. Also, ensure that the SW16 switches on the FPGA are set to ``0101`` to enable QSPI flashing over JTAG (i.e., ``position 1 = 0``, ``position 2 = 1``, ``position 3 = 0``, and ``position 4 = 1``. Having the switch set to the side of the position label indicates 0.) -.. |jtag_help| replace:: JTAG. +.. |fpga_spi_part_number| replace:: ``mt25qu01g-spi-x1_x2_x4_x8`` +.. |mcs_info| replace:: Inside, you will find four files; the ones we are currently interested in will be called ``firesim.mcs`` and ``firesim_secondary.mcs``. Note the full path of the ``firesim.mcs`` and ``firesim_secondary.mcs`` files for the next step. +.. |fpga_attach_prereq| replace:: into an open PCIe slot in the machine. Also, ensure that the SW16 switches on the board are set to ``0101`` to enable QSPI flashing over JTAG (i.e., ``position 1 = 0``, ``position 2 = 1``, ``position 3 = 0``, and ``position 4 = 1``. Having the switch set to the side of the position label indicates 0.) +.. |jtag_help| replace:: JTAG. +.. |extra_mcs| replace:: file from step 7 and for Configuration file 2, choose the ``firesim_secondary.mcs`` file from step 7. +.. |dip_switch_extra| replace:: power). Then, set the SW16 switches on the board to ``0001`` to set the board to automatically program the FPGA from the QSPI at boot (i.e., ``position 1 = 0``, ``position 2 = 0``, ``position 3 = 0``, and ``position 4 = 1``. Having the switch set to the side of the position label indicates 0.) .. |nitefury_patch_xdma| replace:: The directory you are now in contains the XDMA kernel module. Now, let's build and install it: +.. |jtag_cable_reminder| replace:: If necessary, you can remove the USB cable for JTAG (the FPGA is programmed through PCIe for FireSim simulations on the Xilinx VCU118). However, we still recommend leaving the cable attached, since it will allow you to re-flash the SPI in case there are issues. .. include:: Xilinx-XDMA-Template.rst diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-XDMA-Template.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-XDMA-Template.rst index 041854b8..514456e8 100644 --- a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-XDMA-Template.rst +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Initial-Setup/Xilinx-XDMA-Template.rst @@ -159,7 +159,7 @@ Now, test that the module can be inserted: The second command above should have produced output indicating that the XVSEC -driver is loaded. +driver is loaded. Also, make sure you get output for the following (usually, ``/usr/local/sbin/xvsecctl``): @@ -187,25 +187,24 @@ Now, let's attach your |fpga_name|_ FPGA(s) to your Run Farm Machines: 6. Obtain an existing bitstream tar file for your FPGA by opening the ``bitstream_tar`` URL listed under |hwdb_entry_name| in the following file: :gh-file-ref:`deploy/sample-backup-configs/sample_config_hwdb.yaml`. -7. Extract the ``.tar.gz`` file to a known location. Inside, you will find - three files; the one we are currently interested in will be called - ``firesim.mcs``. Note the full path of this ``firesim.mcs`` file for the - next step. +7. Extract the ``.tar.gz`` file to a known location. |mcs_info| 8. Open Vivado Lab and click "Open Hardware Manager". Then click "Open Target" and "Auto connect". 9. Right-click on your FPGA and click "Add Configuration Memory Device". For a |fpga_name|_, choose |fpga_spi_part_number| as the Configuration Memory Part. Click "OK" when prompted to program the configuration memory device. -10. For Configuration file, choose the ``firesim.mcs`` file from step 7. +10. For Configuration file, choose the ``firesim.mcs`` |extra_mcs| 11. Uncheck "Verify" and click OK. -12. When programming the configuration memory device is completed, power off your machine fully (i.e., the FPGA should completely lose power). +12. Right-click on your FPGA and click "Boot from Configuration Memory Device". -13. Cold-boot the machine. A cold boot is required for the FPGA to be successfully re-programmed from its flash. +13. When programming the configuration memory device is completed, power off your machine fully (i.e., the FPGA should completely lose |dip_switch_extra|) -14. Once the machine has booted, run the following to ensure that your FPGA is set up properly: +14. Cold-boot the machine. A cold boot is required for the FPGA to be successfully re-programmed from its flash. + +15. Once the machine has booted, run the following to ensure that your FPGA is set up properly: .. code-block:: bash @@ -215,6 +214,8 @@ If successful, this should show an entry with Xilinx as the manufacturer and two memory regions. There should be one entry for each FPGA you've added to the Run Farm Machine. +.. note:: |jtag_cable_reminder| + 6. Install sshd ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -338,12 +339,12 @@ Then, reboot your machine. Finally, let's ensure that the |tool_type_lab| tools are properly sourced in your shell setup (i.e. ``.bashrc``) so that any shell on your Run Farm Machines can use the corresponding programs. The environment variables should be -visible to any non-interactive shells that are spawned. +visible to any non-interactive shells that are spawned. You can check this by running the following on the Manager Machine, replacing ``RUN_FARM_IP`` with ``localhost`` if your Run Farm machine -and Manager machine are the same machine, or replacing it with the Run Farm -machine's IP address if they are different machines. +and Manager machine are the same machine, or replacing it with the Run Farm +machine's IP address if they are different machines. .. code-block:: bash @@ -358,4 +359,3 @@ each Run Farm machine, replacing ``RUN_FARM_IP`` with a different Run Farm Machi IP address. Congratulations! We've now set up your machine/cluster to run simulations. Click Next to continue with the guide. - diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Repo-Setup/Xilinx-Alveo-U200.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Repo-Setup/Xilinx-Alveo-U200.rst new file mode 100644 index 00000000..cb7203c3 --- /dev/null +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Repo-Setup/Xilinx-Alveo-U200.rst @@ -0,0 +1,11 @@ +.. |fpga_name| replace:: Xilinx Alveo U200 +.. _fpga_name: https://www.xilinx.com/products/boards-and-kits/alveo/u200.html +.. |hwdb_entry_name| replace:: ``alveo_u200_firesim_rocket_singlecore_no_nic`` +.. |platform_name| replace:: xilinx_alveo_u200 +.. |board_name| replace:: au200 +.. |tool_type| replace:: Xilinx Vivado +.. |tool_type_lab| replace:: Xilinx Vivado Lab +.. |example_var| replace:: ``XILINX_VIVADO`` +.. |deploy_manager_code| replace:: ``XilinxAlveoU200InstanceDeployManager`` + +.. include:: Xilinx-XDMA-Template.rst diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Running-Simulations/DOCS_EXAMPLE_config_runtime.yaml b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Running-Simulations/DOCS_EXAMPLE_config_runtime.yaml index 4a6e9968..32756878 100644 --- a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Running-Simulations/DOCS_EXAMPLE_config_runtime.yaml +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Running-Simulations/DOCS_EXAMPLE_config_runtime.yaml @@ -9,7 +9,7 @@ run_farm: default_platform: VitisInstanceDeployManager # REQUIRED: default directory where simulations are run out of on the run farm hosts - default_simulation_dir: /vm/home/buildbot/FIRESIM_RUNS_DIR + default_simulation_dir: /home/buildbot/FIRESIM_RUNS_DIR # REQUIRED: List of unique hostnames/IP addresses, each with their # corresponding specification that describes the properties of the host. diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Running-Simulations/Running-Single-Node-Simulation-Xilinx-Alveo-U200.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Running-Simulations/Running-Single-Node-Simulation-Xilinx-Alveo-U200.rst new file mode 100644 index 00000000..5939e0f2 --- /dev/null +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Running-Simulations/Running-Single-Node-Simulation-Xilinx-Alveo-U200.rst @@ -0,0 +1,7 @@ +.. |fpga_type| replace:: Xilinx Alveo U200 +.. |deploy_manager| replace:: XilinxAlveoU200InstanceDeployManager +.. |deploy_manager_code| replace:: ``XilinxAlveoU200InstanceDeployManager`` +.. |runner| replace:: Xilinx Vivado +.. |hwdb_entry_name| replace:: alveo_u200_firesim_rocket_singlecore_no_nic + +.. include:: Running-Single-Node-Simulation-Template.rst diff --git a/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U200-FPGAs.rst b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U200-FPGAs.rst new file mode 100644 index 00000000..dd734d57 --- /dev/null +++ b/docs/Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U200-FPGAs.rst @@ -0,0 +1,17 @@ +.. |fpga_name| replace:: Xilinx Alveo U200 XDMA-based +.. |fpga_name_short| replace:: Xilinx Alveo U200 +.. _fpga_name_short: https://www.xilinx.com/products/boards-and-kits/alveo/u200.html +.. |flow_name| replace:: XDMA-based +.. |build_type| replace:: Xilinx Vivado + +.. _u200-standard-flow: + +.. include:: Intro-Template.rst + +.. toctree:: + :maxdepth: 3 + + Initial-Setup/Xilinx-Alveo-U200 + Repo-Setup/Xilinx-Alveo-U200 + Running-Simulations/Running-Single-Node-Simulation-Xilinx-Alveo-U200 + Building-a-FireSim-Bitstream/Xilinx-Alveo-U200 diff --git a/docs/index.rst b/docs/index.rst index dc373529..3cbc8a0b 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -10,6 +10,7 @@ New to FireSim? Jump to the :doc:`/FireSim-Basics` page for more info. FireSim-Basics Getting-Started-Guides/AWS-EC2-F1-Getting-Started/index + Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U200-FPGAs Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U250-FPGAs Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-Alveo-U280-FPGAs Getting-Started-Guides/On-Premises-FPGA-Getting-Started/Xilinx-VCU118-FPGAs diff --git a/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2021.1.tcl b/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2021.1.tcl index ab7ea16f..8f65fed3 100644 --- a/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2021.1.tcl +++ b/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2021.1.tcl @@ -34,7 +34,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { # START ################################################################ -# The design that will be created by this Tcl script contains the following +# The design that will be created by this Tcl script contains the following # module references: # axi_tieoff_master, firesim_wrapper @@ -81,7 +81,7 @@ if { ${design_name} eq "" } { set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." set nRet 1 } elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: + # USE CASES: # 6) Current opened design, has components, but diff names, design_name exists in project. # 7) No opened design, design_name exists in project. @@ -115,7 +115,7 @@ set bCheckIPsPassed 1 ################################################################## set bCheckIPs 1 if { $bCheckIPs == 1 } { - set list_check_ips "\ + set list_check_ips "\ xilinx.com:ip:axi_clock_converter:2.1\ xilinx.com:ip:axi_dwidth_converter:2.1\ xilinx.com:ip:ddr4:2.2\ @@ -148,7 +148,7 @@ xilinx.com:ip:xlconstant:1.1\ ################################################################## set bCheckModules 1 if { $bCheckModules == 1 } { - set list_check_mods "\ + set list_check_mods "\ axi_tieoff_master\ firesim_wrapper\ " @@ -266,7 +266,7 @@ proc create_root_design { parentCell firesim_freq } { catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } - + # Create instance: ddr4_0, and set properties set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] set_property -dict [ list \ @@ -289,7 +289,7 @@ proc create_root_design { parentCell firesim_freq } { catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } - + # Create instance: proc_sys_reset_0, and set properties set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] diff --git a/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2022.1.tcl b/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2022.1.tcl new file mode 100644 index 00000000..e73afbf8 --- /dev/null +++ b/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2022.1.tcl @@ -0,0 +1,386 @@ +################################################################ +# This is a generated script based on design: design_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2022.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# The design that will be created by this Tcl script contains the following +# module references: +# axi_tieoff_master, firesim_wrapper + +# Please add the sources of those modules before sourcing this Tcl script. + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name design_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_clock_converter:2.1\ +xilinx.com:ip:axi_dwidth_converter:2.1\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:ddr4:2.2\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:util_vector_logic:2.0\ +xilinx.com:ip:util_ds_buf:2.2\ +xilinx.com:ip:xdma:4.1\ +xilinx.com:ip:xlconstant:1.1\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +axi_tieoff_master\ +firesim_wrapper\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell firesim_freq } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr4_sdram_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c0 ] + + set default_300mhz_clk0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_300mhz_clk0 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {300000000} \ + ] $default_300mhz_clk0 + + set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $pcie_refclk + + + # Create ports + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $pcie_perstn + set resetn [ create_bd_port -dir I -type rst resetn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $resetn + + # Create instance: axi_clock_converter_0, and set properties + set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ] + + # Create instance: axi_clock_converter_1, and set properties + set axi_clock_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_1 ] + + # Create instance: axi_dwidth_converter_0, and set properties + set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ] + set_property -dict [list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {512} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.SI_ID_WIDTH {16} \ + ] $axi_dwidth_converter_0 + + + # Create instance: axi_tieoff_master_0, and set properties + set block_name axi_tieoff_master + set block_cell_name axi_tieoff_master_0 + if { [catch {set axi_tieoff_master_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $axi_tieoff_master_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: clk_wiz_0, and set properties + set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] + set_property -dict [list \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ $firesim_freq \ + CONFIG.USE_LOCKED {false} \ + ] $clk_wiz_0 + + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_AxiAddressWidth {34} \ + CONFIG.C0.DDR4_EN_PARITY {true} \ + CONFIG.C0.DDR4_MCS_ECC {false} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ + CONFIG.C0_CLOCK_BOARD_INTERFACE {default_300mhz_clk0} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0} \ + CONFIG.Debug_Signal {Disable} \ + CONFIG.RESET_BOARD_INTERFACE {resetn} \ + ] $ddr4_0 + + + # Create instance: firesim_wrapper_0, and set properties + set block_name firesim_wrapper + set block_cell_name firesim_wrapper_0 + if { [catch {set firesim_wrapper_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $firesim_wrapper_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: proc_sys_reset_1, and set properties + set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] + + # Create instance: resetn_inv_0, and set properties + set resetn_inv_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 resetn_inv_0 ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $resetn_inv_0 + + + # Create instance: util_ds_buf, and set properties + set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ] + set_property -dict [list \ + CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $util_ds_buf + + + # Create instance: xdma_0, and set properties + set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ] + set_property -dict [list \ + CONFIG.PCIE_BOARD_INTERFACE {pci_express_x16} \ + CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \ + CONFIG.axilite_master_en {true} \ + CONFIG.axilite_master_size {32} \ + CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \ + CONFIG.xdma_rnum_chnl {4} \ + CONFIG.xdma_wnum_chnl {4} \ + ] $xdma_0 + + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property CONFIG.CONST_VAL {0} $xlconstant_0 + + + # Create interface connections + connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_DMA] + connect_bd_intf_net -intf_net axi_clock_converter_1_M_AXI [get_bd_intf_pins axi_clock_converter_1/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_CTRL] + connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] + connect_bd_intf_net -intf_net axi_tieoff_master_0_TIEOFF_M_AXI_CTRL_0 [get_bd_intf_pins axi_tieoff_master_0/TIEOFF_M_AXI_CTRL_0] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram_c0] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net default_300mhz_clk0_1 [get_bd_intf_ports default_300mhz_clk0] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net firesim_wrapper_0_M_AXI_DDR0 [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins firesim_wrapper_0/M_AXI_DDR0] + connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D] + connect_bd_intf_net -intf_net xdma_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins xdma_0/M_AXI] + connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins axi_clock_converter_1/S_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE] + connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins xdma_0/pcie_mgt] + + # Create port connections + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_dwidth_converter_0/m_axi_aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] + connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins xdma_0/sys_rst_n] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins firesim_wrapper_0/sys_reset_n] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] + connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins resetn_inv_0/Op1] + connect_bd_net -net resetn_inv_0_Res [get_bd_pins clk_wiz_0/reset] [get_bd_pins ddr4_0/sys_rst] [get_bd_pins resetn_inv_0/Res] + connect_bd_net -net rst_ddr4_0_300M_interconnect_aresetn [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] + connect_bd_net -net sys_clk_30 [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins firesim_wrapper_0/sys_clk_30] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] + connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk] + connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins util_ds_buf/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt] + connect_bd_net -net xdma_0_axi_aclk [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins xdma_0/axi_aclk] + connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins xdma_0/axi_aresetn] + connect_bd_net -net xlconstant_0_dout [get_bd_pins xdma_0/usr_irq_req] [get_bd_pins xlconstant_0/dout] + + # Create address segments + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" $desired_host_frequency diff --git a/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2022.2.tcl b/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2022.2.tcl index cb327b54..c31714b4 100644 --- a/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2022.2.tcl +++ b/platforms/xilinx_alveo_u200/cl_firesim/scripts/create_bd_2022.2.tcl @@ -34,7 +34,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { # START ################################################################ -# The design that will be created by this Tcl script contains the following +# The design that will be created by this Tcl script contains the following # module references: # axi_tieoff_master, firesim_wrapper @@ -81,7 +81,7 @@ if { ${design_name} eq "" } { set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." set nRet 1 } elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: + # USE CASES: # 6) Current opened design, has components, but diff names, design_name exists in project. # 7) No opened design, design_name exists in project. @@ -115,7 +115,7 @@ set bCheckIPsPassed 1 ################################################################## set bCheckIPs 1 if { $bCheckIPs == 1 } { - set list_check_ips "\ + set list_check_ips "\ xilinx.com:ip:axi_clock_converter:2.1\ xilinx.com:ip:axi_dwidth_converter:2.1\ xilinx.com:ip:clk_wiz:6.0\ @@ -149,7 +149,7 @@ xilinx.com:ip:xlconstant:1.1\ ################################################################## set bCheckModules 1 if { $bCheckModules == 1 } { - set list_check_mods "\ + set list_check_mods "\ axi_tieoff_master\ firesim_wrapper\ " @@ -266,7 +266,7 @@ proc create_root_design { parentCell firesim_freq } { catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } - + # Create instance: clk_wiz_0, and set properties set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] set_property -dict [list \ @@ -301,7 +301,7 @@ proc create_root_design { parentCell firesim_freq } { catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } - + # Create instance: proc_sys_reset_0, and set properties set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] diff --git a/platforms/xilinx_alveo_u200/cl_firesim/scripts/implementation_2022.1.tcl b/platforms/xilinx_alveo_u200/cl_firesim/scripts/implementation_2022.1.tcl new file mode 120000 index 00000000..b58711f4 --- /dev/null +++ b/platforms/xilinx_alveo_u200/cl_firesim/scripts/implementation_2022.1.tcl @@ -0,0 +1 @@ +../../../xilinx_alveo_u250/cl_firesim/scripts/implementation_2022.1.tcl \ No newline at end of file diff --git a/platforms/xilinx_alveo_u200/cl_firesim/scripts/platform_env.tcl b/platforms/xilinx_alveo_u200/cl_firesim/scripts/platform_env.tcl index e8fc14de..84ef64ea 100644 --- a/platforms/xilinx_alveo_u200/cl_firesim/scripts/platform_env.tcl +++ b/platforms/xilinx_alveo_u200/cl_firesim/scripts/platform_env.tcl @@ -1 +1 @@ -set jobs 12 +set jobs 8 diff --git a/platforms/xilinx_alveo_u250/cl_firesim/scripts/create_bd_2021.1.tcl b/platforms/xilinx_alveo_u250/cl_firesim/scripts/create_bd_2021.1.tcl index ab7ea16f..8f65fed3 100644 --- a/platforms/xilinx_alveo_u250/cl_firesim/scripts/create_bd_2021.1.tcl +++ b/platforms/xilinx_alveo_u250/cl_firesim/scripts/create_bd_2021.1.tcl @@ -34,7 +34,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { # START ################################################################ -# The design that will be created by this Tcl script contains the following +# The design that will be created by this Tcl script contains the following # module references: # axi_tieoff_master, firesim_wrapper @@ -81,7 +81,7 @@ if { ${design_name} eq "" } { set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." set nRet 1 } elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: + # USE CASES: # 6) Current opened design, has components, but diff names, design_name exists in project. # 7) No opened design, design_name exists in project. @@ -115,7 +115,7 @@ set bCheckIPsPassed 1 ################################################################## set bCheckIPs 1 if { $bCheckIPs == 1 } { - set list_check_ips "\ + set list_check_ips "\ xilinx.com:ip:axi_clock_converter:2.1\ xilinx.com:ip:axi_dwidth_converter:2.1\ xilinx.com:ip:ddr4:2.2\ @@ -148,7 +148,7 @@ xilinx.com:ip:xlconstant:1.1\ ################################################################## set bCheckModules 1 if { $bCheckModules == 1 } { - set list_check_mods "\ + set list_check_mods "\ axi_tieoff_master\ firesim_wrapper\ " @@ -266,7 +266,7 @@ proc create_root_design { parentCell firesim_freq } { catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } - + # Create instance: ddr4_0, and set properties set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] set_property -dict [ list \ @@ -289,7 +289,7 @@ proc create_root_design { parentCell firesim_freq } { catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } - + # Create instance: proc_sys_reset_0, and set properties set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] diff --git a/platforms/xilinx_alveo_u250/cl_firesim/scripts/create_bd_2022.1.tcl b/platforms/xilinx_alveo_u250/cl_firesim/scripts/create_bd_2022.1.tcl new file mode 100644 index 00000000..e73afbf8 --- /dev/null +++ b/platforms/xilinx_alveo_u250/cl_firesim/scripts/create_bd_2022.1.tcl @@ -0,0 +1,386 @@ +################################################################ +# This is a generated script based on design: design_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2022.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# The design that will be created by this Tcl script contains the following +# module references: +# axi_tieoff_master, firesim_wrapper + +# Please add the sources of those modules before sourcing this Tcl script. + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name design_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_clock_converter:2.1\ +xilinx.com:ip:axi_dwidth_converter:2.1\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:ddr4:2.2\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:util_vector_logic:2.0\ +xilinx.com:ip:util_ds_buf:2.2\ +xilinx.com:ip:xdma:4.1\ +xilinx.com:ip:xlconstant:1.1\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +axi_tieoff_master\ +firesim_wrapper\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell firesim_freq } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr4_sdram_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c0 ] + + set default_300mhz_clk0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_300mhz_clk0 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {300000000} \ + ] $default_300mhz_clk0 + + set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $pcie_refclk + + + # Create ports + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $pcie_perstn + set resetn [ create_bd_port -dir I -type rst resetn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $resetn + + # Create instance: axi_clock_converter_0, and set properties + set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ] + + # Create instance: axi_clock_converter_1, and set properties + set axi_clock_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_1 ] + + # Create instance: axi_dwidth_converter_0, and set properties + set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ] + set_property -dict [list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {512} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.SI_ID_WIDTH {16} \ + ] $axi_dwidth_converter_0 + + + # Create instance: axi_tieoff_master_0, and set properties + set block_name axi_tieoff_master + set block_cell_name axi_tieoff_master_0 + if { [catch {set axi_tieoff_master_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $axi_tieoff_master_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: clk_wiz_0, and set properties + set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] + set_property -dict [list \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ $firesim_freq \ + CONFIG.USE_LOCKED {false} \ + ] $clk_wiz_0 + + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_AxiAddressWidth {34} \ + CONFIG.C0.DDR4_EN_PARITY {true} \ + CONFIG.C0.DDR4_MCS_ECC {false} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ + CONFIG.C0_CLOCK_BOARD_INTERFACE {default_300mhz_clk0} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0} \ + CONFIG.Debug_Signal {Disable} \ + CONFIG.RESET_BOARD_INTERFACE {resetn} \ + ] $ddr4_0 + + + # Create instance: firesim_wrapper_0, and set properties + set block_name firesim_wrapper + set block_cell_name firesim_wrapper_0 + if { [catch {set firesim_wrapper_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $firesim_wrapper_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: proc_sys_reset_1, and set properties + set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] + + # Create instance: resetn_inv_0, and set properties + set resetn_inv_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 resetn_inv_0 ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $resetn_inv_0 + + + # Create instance: util_ds_buf, and set properties + set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ] + set_property -dict [list \ + CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $util_ds_buf + + + # Create instance: xdma_0, and set properties + set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ] + set_property -dict [list \ + CONFIG.PCIE_BOARD_INTERFACE {pci_express_x16} \ + CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \ + CONFIG.axilite_master_en {true} \ + CONFIG.axilite_master_size {32} \ + CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \ + CONFIG.xdma_rnum_chnl {4} \ + CONFIG.xdma_wnum_chnl {4} \ + ] $xdma_0 + + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property CONFIG.CONST_VAL {0} $xlconstant_0 + + + # Create interface connections + connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_DMA] + connect_bd_intf_net -intf_net axi_clock_converter_1_M_AXI [get_bd_intf_pins axi_clock_converter_1/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_CTRL] + connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] + connect_bd_intf_net -intf_net axi_tieoff_master_0_TIEOFF_M_AXI_CTRL_0 [get_bd_intf_pins axi_tieoff_master_0/TIEOFF_M_AXI_CTRL_0] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram_c0] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net default_300mhz_clk0_1 [get_bd_intf_ports default_300mhz_clk0] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net firesim_wrapper_0_M_AXI_DDR0 [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins firesim_wrapper_0/M_AXI_DDR0] + connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D] + connect_bd_intf_net -intf_net xdma_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins xdma_0/M_AXI] + connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins axi_clock_converter_1/S_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE] + connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins xdma_0/pcie_mgt] + + # Create port connections + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_dwidth_converter_0/m_axi_aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] + connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins xdma_0/sys_rst_n] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins firesim_wrapper_0/sys_reset_n] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] + connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins resetn_inv_0/Op1] + connect_bd_net -net resetn_inv_0_Res [get_bd_pins clk_wiz_0/reset] [get_bd_pins ddr4_0/sys_rst] [get_bd_pins resetn_inv_0/Res] + connect_bd_net -net rst_ddr4_0_300M_interconnect_aresetn [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] + connect_bd_net -net sys_clk_30 [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins firesim_wrapper_0/sys_clk_30] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] + connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk] + connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins util_ds_buf/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt] + connect_bd_net -net xdma_0_axi_aclk [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins xdma_0/axi_aclk] + connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins xdma_0/axi_aresetn] + connect_bd_net -net xlconstant_0_dout [get_bd_pins xdma_0/usr_irq_req] [get_bd_pins xlconstant_0/dout] + + # Create address segments + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" $desired_host_frequency diff --git a/platforms/xilinx_alveo_u250/cl_firesim/scripts/create_bd_2022.2.tcl b/platforms/xilinx_alveo_u250/cl_firesim/scripts/create_bd_2022.2.tcl index cb327b54..c31714b4 100644 --- a/platforms/xilinx_alveo_u250/cl_firesim/scripts/create_bd_2022.2.tcl +++ b/platforms/xilinx_alveo_u250/cl_firesim/scripts/create_bd_2022.2.tcl @@ -34,7 +34,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { # START ################################################################ -# The design that will be created by this Tcl script contains the following +# The design that will be created by this Tcl script contains the following # module references: # axi_tieoff_master, firesim_wrapper @@ -81,7 +81,7 @@ if { ${design_name} eq "" } { set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." set nRet 1 } elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: + # USE CASES: # 6) Current opened design, has components, but diff names, design_name exists in project. # 7) No opened design, design_name exists in project. @@ -115,7 +115,7 @@ set bCheckIPsPassed 1 ################################################################## set bCheckIPs 1 if { $bCheckIPs == 1 } { - set list_check_ips "\ + set list_check_ips "\ xilinx.com:ip:axi_clock_converter:2.1\ xilinx.com:ip:axi_dwidth_converter:2.1\ xilinx.com:ip:clk_wiz:6.0\ @@ -149,7 +149,7 @@ xilinx.com:ip:xlconstant:1.1\ ################################################################## set bCheckModules 1 if { $bCheckModules == 1 } { - set list_check_mods "\ + set list_check_mods "\ axi_tieoff_master\ firesim_wrapper\ " @@ -266,7 +266,7 @@ proc create_root_design { parentCell firesim_freq } { catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } - + # Create instance: clk_wiz_0, and set properties set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] set_property -dict [list \ @@ -301,7 +301,7 @@ proc create_root_design { parentCell firesim_freq } { catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } - + # Create instance: proc_sys_reset_0, and set properties set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] diff --git a/platforms/xilinx_alveo_u250/cl_firesim/scripts/implementation_2022.1.tcl b/platforms/xilinx_alveo_u250/cl_firesim/scripts/implementation_2022.1.tcl new file mode 120000 index 00000000..e06ec071 --- /dev/null +++ b/platforms/xilinx_alveo_u250/cl_firesim/scripts/implementation_2022.1.tcl @@ -0,0 +1 @@ +implementation_2022.2.tcl \ No newline at end of file diff --git a/platforms/xilinx_alveo_u250/cl_firesim/scripts/implementation_idr_2022.1.tcl b/platforms/xilinx_alveo_u250/cl_firesim/scripts/implementation_idr_2022.1.tcl new file mode 120000 index 00000000..e55c4c12 --- /dev/null +++ b/platforms/xilinx_alveo_u250/cl_firesim/scripts/implementation_idr_2022.1.tcl @@ -0,0 +1 @@ +implementation_idr_2022.2.tcl \ No newline at end of file diff --git a/platforms/xilinx_alveo_u250/cl_firesim/scripts/platform_env.tcl b/platforms/xilinx_alveo_u250/cl_firesim/scripts/platform_env.tcl index e8fc14de..84ef64ea 100644 --- a/platforms/xilinx_alveo_u250/cl_firesim/scripts/platform_env.tcl +++ b/platforms/xilinx_alveo_u250/cl_firesim/scripts/platform_env.tcl @@ -1 +1 @@ -set jobs 12 +set jobs 8 diff --git a/platforms/xilinx_alveo_u250/scripts/pcielib.py b/platforms/xilinx_alveo_u250/scripts/pcielib.py index 528dc01d..1d9ac44f 100644 --- a/platforms/xilinx_alveo_u250/scripts/pcielib.py +++ b/platforms/xilinx_alveo_u250/scripts/pcielib.py @@ -1,6 +1,7 @@ import subprocess import sys import re +import time from pathlib import Path from typing import Dict, List @@ -102,6 +103,7 @@ def clear_serr_bits(bus_id: str) -> None: run = subprocess.run(['setpci', '-s', bridgeBDF, 'COMMAND=0000:0100']) if run.returncode != 0: sys.exit(f":ERROR: Unable to clear SERR bit for {bridgeBDF}") + time.sleep(1) # clear fatal error reporting enable bit in the device control register # https://support.xilinx.com/s/question/0D52E00006hpjPHSAY/dell-r720-poweredge-server-reboots-on-fpga-reprogramming?language=en_US @@ -110,6 +112,7 @@ def clear_fatal_error_reporting_bits(bus_id: str) -> None: run = subprocess.run(['setpci', '-s', bridgeBDF, 'CAP_EXP+8.w=0000:0004']) if run.returncode != 0: sys.exit(f":ERROR: Unable to clear error reporting bit for {bridgeBDF}") + time.sleep(1) def write_to_linux_device_path(path: Path, data: str = '1\n') -> None: try: @@ -117,6 +120,7 @@ def write_to_linux_device_path(path: Path, data: str = '1\n') -> None: open(path, 'w').write(data) except: sys.exit(f":ERROR: Cannot write to {path} value: {data}") + time.sleep(1) def remove(bus_id: str) -> None: for devicePaths in get_device_paths(bus_id): @@ -138,6 +142,7 @@ def enable_memmapped_transfers(bus_id: str) -> None: run = subprocess.run(['setpci', '-s', deviceBDF, 'COMMAND=0x02']) if run.returncode != 0: sys.exit(f":ERROR: Unable to enable memmapped transfers on {deviceBDF}") + time.sleep(1) def any_device_exists(bus_id: str) -> bool: return len(get_device_paths(bus_id)) > 0 diff --git a/platforms/xilinx_alveo_u280/cl_firesim/scripts/create_bd_2021.1.tcl b/platforms/xilinx_alveo_u280/cl_firesim/scripts/create_bd_2021.1.tcl index 805f9211..82d32ee7 100644 --- a/platforms/xilinx_alveo_u280/cl_firesim/scripts/create_bd_2021.1.tcl +++ b/platforms/xilinx_alveo_u280/cl_firesim/scripts/create_bd_2021.1.tcl @@ -34,7 +34,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { # START ################################################################ -# The design that will be created by this Tcl script contains the following +# The design that will be created by this Tcl script contains the following # module references: # axi_tieoff_master, firesim_wrapper @@ -81,7 +81,7 @@ if { ${design_name} eq "" } { set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." set nRet 1 } elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: + # USE CASES: # 6) Current opened design, has components, but diff names, design_name exists in project. # 7) No opened design, design_name exists in project. @@ -115,7 +115,7 @@ set bCheckIPsPassed 1 ################################################################## set bCheckIPs 1 if { $bCheckIPs == 1 } { - set list_check_ips "\ + set list_check_ips "\ xilinx.com:ip:axi_clock_converter:2.1\ xilinx.com:ip:axi_dwidth_converter:2.1\ xilinx.com:ip:clk_wiz:6.0\ @@ -149,7 +149,7 @@ xilinx.com:ip:xlconstant:1.1\ ################################################################## set bCheckModules 1 if { $bCheckModules == 1 } { - set list_check_mods "\ + set list_check_mods "\ axi_tieoff_master\ firesim_wrapper\ " @@ -265,7 +265,7 @@ proc create_root_design { parentCell firesim_freq } { catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } - + # Create instance: clk_wiz_0, and set properties set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] set_property -dict [ list \ @@ -295,7 +295,7 @@ proc create_root_design { parentCell firesim_freq } { catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } - + # Create instance: proc_sys_reset_0, and set properties set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] diff --git a/platforms/xilinx_alveo_u280/cl_firesim/scripts/create_bd_2022.1.tcl b/platforms/xilinx_alveo_u280/cl_firesim/scripts/create_bd_2022.1.tcl new file mode 100644 index 00000000..81b5c2b3 --- /dev/null +++ b/platforms/xilinx_alveo_u280/cl_firesim/scripts/create_bd_2022.1.tcl @@ -0,0 +1,387 @@ +################################################################ +# This is a generated script based on design: design_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2022.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + + +# The design that will be created by this Tcl script contains the following +# module references: +# axi_tieoff_master, firesim_wrapper + +# Please add the sources of those modules before sourcing this Tcl script. + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name design_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_clock_converter:2.1\ +xilinx.com:ip:axi_dwidth_converter:2.1\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:ddr4:2.2\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:util_vector_logic:2.0\ +xilinx.com:ip:util_ds_buf:2.2\ +xilinx.com:ip:xdma:4.1\ +xilinx.com:ip:xlconstant:1.1\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +axi_tieoff_master\ +firesim_wrapper\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell firesim_freq } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr4_sdram_c0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c0 ] + + set sysclk0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sysclk0 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $sysclk0 + + set pci_express_x16 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x16 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $pcie_refclk + + + # Create ports + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $pcie_perstn + set resetn [ create_bd_port -dir I -type rst resetn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $resetn + + # Create instance: axi_clock_converter_0, and set properties + set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ] + + # Create instance: axi_clock_converter_1, and set properties + set axi_clock_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_1 ] + + # Create instance: axi_dwidth_converter_0, and set properties + set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ] + set_property -dict [list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {512} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.SI_ID_WIDTH {16} \ + ] $axi_dwidth_converter_0 + + + # Create instance: axi_tieoff_master_0, and set properties + set block_name axi_tieoff_master + set block_cell_name axi_tieoff_master_0 + if { [catch {set axi_tieoff_master_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $axi_tieoff_master_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: clk_wiz_0, and set properties + set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] + set_property -dict [list \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ $firesim_freq \ + CONFIG.USE_LOCKED {false} \ + ] $clk_wiz_0 + + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_AxiAddressWidth {34} \ + CONFIG.C0.DDR4_EN_PARITY {true} \ + CONFIG.C0.DDR4_MCS_ECC {false} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ + CONFIG.C0_CLOCK_BOARD_INTERFACE {sysclk0} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0} \ + CONFIG.Debug_Signal {Disable} \ + CONFIG.RESET_BOARD_INTERFACE {resetn} \ + ] $ddr4_0 + + + # Create instance: firesim_wrapper_0, and set properties + set block_name firesim_wrapper + set block_cell_name firesim_wrapper_0 + if { [catch {set firesim_wrapper_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $firesim_wrapper_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: proc_sys_reset_1, and set properties + set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] + + # Create instance: resetn_inv_0, and set properties + set resetn_inv_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 resetn_inv_0 ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $resetn_inv_0 + + + # Create instance: util_ds_buf, and set properties + set util_ds_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf ] + set_property -dict [list \ + CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $util_ds_buf + + + # Create instance: xdma_0, and set properties + set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ] + set_property -dict [list \ + CONFIG.PCIE_BOARD_INTERFACE {pci_express_x16} \ + CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \ + CONFIG.axilite_master_en {true} \ + CONFIG.axilite_master_size {32} \ + CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \ + CONFIG.xdma_rnum_chnl {4} \ + CONFIG.xdma_wnum_chnl {4} \ + ] $xdma_0 + + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property CONFIG.CONST_VAL {0} $xlconstant_0 + + + # Create interface connections + connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_DMA] + connect_bd_intf_net -intf_net axi_clock_converter_1_M_AXI [get_bd_intf_pins axi_clock_converter_1/M_AXI] [get_bd_intf_pins firesim_wrapper_0/S_AXI_CTRL] + connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] + connect_bd_intf_net -intf_net axi_tieoff_master_0_TIEOFF_M_AXI_CTRL_0 [get_bd_intf_pins axi_tieoff_master_0/TIEOFF_M_AXI_CTRL_0] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram_c0] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net sysclk0_1 [get_bd_intf_ports sysclk0] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net firesim_wrapper_0_M_AXI_DDR0 [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins firesim_wrapper_0/M_AXI_DDR0] + connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf/CLK_IN_D] + connect_bd_intf_net -intf_net xdma_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins xdma_0/M_AXI] + connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins axi_clock_converter_1/S_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE] + connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x16] [get_bd_intf_pins xdma_0/pcie_mgt] + + # Create port connections + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_dwidth_converter_0/m_axi_aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] + connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins xdma_0/sys_rst_n] + connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins firesim_wrapper_0/sys_reset_n] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] + connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins resetn_inv_0/Op1] + connect_bd_net -net resetn_inv_0_Res [get_bd_pins clk_wiz_0/reset] [get_bd_pins ddr4_0/sys_rst] [get_bd_pins resetn_inv_0/Res] + connect_bd_net -net rst_ddr4_0_100M_interconnect_aresetn [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] + connect_bd_net -net sys_clk_30 [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins firesim_wrapper_0/sys_clk_30] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] + connect_bd_net -net util_ds_buf_IBUF_DS_ODIV2 [get_bd_pins util_ds_buf/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk] + connect_bd_net -net util_ds_buf_IBUF_OUT [get_bd_pins util_ds_buf/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt] + connect_bd_net -net xdma_0_axi_aclk [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins xdma_0/axi_aclk] + connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins xdma_0/axi_aresetn] + connect_bd_net -net xlconstant_0_dout [get_bd_pins xdma_0/usr_irq_req] [get_bd_pins xlconstant_0/dout] + + # Create address segments + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" $desired_host_frequency diff --git a/platforms/xilinx_alveo_u280/cl_firesim/scripts/create_bd_2022.2.tcl b/platforms/xilinx_alveo_u280/cl_firesim/scripts/create_bd_2022.2.tcl index 720e6f15..e06661db 100644 --- a/platforms/xilinx_alveo_u280/cl_firesim/scripts/create_bd_2022.2.tcl +++ b/platforms/xilinx_alveo_u280/cl_firesim/scripts/create_bd_2022.2.tcl @@ -35,7 +35,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { ################################################################ -# The design that will be created by this Tcl script contains the following +# The design that will be created by this Tcl script contains the following # module references: # axi_tieoff_master, firesim_wrapper @@ -82,7 +82,7 @@ if { ${design_name} eq "" } { set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." set nRet 1 } elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: + # USE CASES: # 6) Current opened design, has components, but diff names, design_name exists in project. # 7) No opened design, design_name exists in project. @@ -116,7 +116,7 @@ set bCheckIPsPassed 1 ################################################################## set bCheckIPs 1 if { $bCheckIPs == 1 } { - set list_check_ips "\ + set list_check_ips "\ xilinx.com:ip:axi_clock_converter:2.1\ xilinx.com:ip:axi_dwidth_converter:2.1\ xilinx.com:ip:clk_wiz:6.0\ @@ -150,7 +150,7 @@ xilinx.com:ip:xlconstant:1.1\ ################################################################## set bCheckModules 1 if { $bCheckModules == 1 } { - set list_check_mods "\ + set list_check_mods "\ axi_tieoff_master\ firesim_wrapper\ " @@ -267,7 +267,7 @@ proc create_root_design { parentCell firesim_freq } { catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } - + # Create instance: clk_wiz_0, and set properties set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] set_property -dict [list \ @@ -302,7 +302,7 @@ proc create_root_design { parentCell firesim_freq } { catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } - + # Create instance: proc_sys_reset_0, and set properties set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] diff --git a/platforms/xilinx_alveo_u280/cl_firesim/scripts/implementation_2022.1.tcl b/platforms/xilinx_alveo_u280/cl_firesim/scripts/implementation_2022.1.tcl new file mode 120000 index 00000000..b58711f4 --- /dev/null +++ b/platforms/xilinx_alveo_u280/cl_firesim/scripts/implementation_2022.1.tcl @@ -0,0 +1 @@ +../../../xilinx_alveo_u250/cl_firesim/scripts/implementation_2022.1.tcl \ No newline at end of file diff --git a/platforms/xilinx_alveo_u280/cl_firesim/scripts/platform_env.tcl b/platforms/xilinx_alveo_u280/cl_firesim/scripts/platform_env.tcl index e8fc14de..84ef64ea 100644 --- a/platforms/xilinx_alveo_u280/cl_firesim/scripts/platform_env.tcl +++ b/platforms/xilinx_alveo_u280/cl_firesim/scripts/platform_env.tcl @@ -1 +1 @@ -set jobs 12 +set jobs 8 diff --git a/platforms/xilinx_vcu118/build-bitstream.sh b/platforms/xilinx_vcu118/build-bitstream.sh index 371c0c7b..0dcc2b93 100755 --- a/platforms/xilinx_vcu118/build-bitstream.sh +++ b/platforms/xilinx_vcu118/build-bitstream.sh @@ -82,3 +82,4 @@ vivado -mode batch -source ../tcl/build.tcl -tclargs $FREQUENCY $STRATEGY $BOARD mkdir -p ../vivado_proj cp example_pblock_partition_partial.bit ../vivado_proj/firesim.bit cp ../../shell/prebuilt/empty_primary.mcs ../vivado_proj/firesim.mcs +cp ../../shell/prebuilt/empty_secondary.mcs ../vivado_proj/firesim_secondary.mcs diff --git a/platforms/xilinx_vcu118/garnet-firesim b/platforms/xilinx_vcu118/garnet-firesim index 8bf28f59..4e62dfa8 160000 --- a/platforms/xilinx_vcu118/garnet-firesim +++ b/platforms/xilinx_vcu118/garnet-firesim @@ -1 +1 @@ -Subproject commit 8bf28f59b0ef72fd2bc3bce5844ab766fc6c1ddb +Subproject commit 4e62dfa8016402c93f03dd2e0e54270f1c85cfeb diff --git a/scripts/generate-conda-lockfile.sh b/scripts/generate-conda-lockfile.sh index 4ac3a32d..c1806f19 100755 --- a/scripts/generate-conda-lockfile.sh +++ b/scripts/generate-conda-lockfile.sh @@ -6,4 +6,4 @@ if [ ! -d "$REQS_DIR" ]; then echo "$REQS_DIR does not exist, make sure you're calling this script from firesim/" exit 1 fi -conda-lock -f "$REQS_DIR/firesim.yaml" -f "$REQS_DIR/ci-shared.yaml" -p linux-64 --lockfile "$REQS_DIR/conda-reqs.conda-lock.yml" +conda-lock --conda $(which conda) -f "$REQS_DIR/firesim.yaml" -f "$REQS_DIR/ci-shared.yaml" -p linux-64 --lockfile "$REQS_DIR/conda-reqs.conda-lock.yml" diff --git a/sim/build.sbt b/sim/build.sbt index 04af2347..23aa57aa 100644 --- a/sim/build.sbt +++ b/sim/build.sbt @@ -1,6 +1,6 @@ import Tests._ -val chiselVersion = "3.5.6" +val chiselVersion = "3.6.0" // keep chisel/firrtl specific class files, rename other conflicts val chiselFirrtlMergeStrategy = CustomMergeStrategy.rename { dep => diff --git a/sim/midas/src/main/scala/midas/FPGAQoRShimGenerator.scala b/sim/midas/src/main/scala/midas/FPGAQoRShimGenerator.scala index cb933d61..d8c21f59 100644 --- a/sim/midas/src/main/scala/midas/FPGAQoRShimGenerator.scala +++ b/sim/midas/src/main/scala/midas/FPGAQoRShimGenerator.scala @@ -1,4 +1,5 @@ // See LICENSE for license details. + package midas.unittest import chisel3._ @@ -34,4 +35,3 @@ class Midas2QoRTargets extends Config((site, here, up) => { ) } }) - diff --git a/sim/midas/src/main/scala/midas/core/CPUManagedStreamEngine.scala b/sim/midas/src/main/scala/midas/core/CPUManagedStreamEngine.scala index 6377621a..0b78ff02 100644 --- a/sim/midas/src/main/scala/midas/core/CPUManagedStreamEngine.scala +++ b/sim/midas/src/main/scala/midas/core/CPUManagedStreamEngine.scala @@ -1,4 +1,3 @@ - // See LICENSE for license details. package midas.core diff --git a/sim/midas/src/main/scala/midas/core/SimUtils.scala b/sim/midas/src/main/scala/midas/core/SimUtils.scala index 35319854..eed1907f 100644 --- a/sim/midas/src/main/scala/midas/core/SimUtils.scala +++ b/sim/midas/src/main/scala/midas/core/SimUtils.scala @@ -99,7 +99,6 @@ object SimUtils { // Simple wrapper for nested bundles. private class BundleRecord(elms: Seq[(String, Data)]) extends Record { override val elements = ListMap((elms.map { case (name, data) => name -> data.cloneType }):_*) - override def cloneType: this.type = new BundleRecord(elms).asInstanceOf[this.type] override def toString: String = s"{${elements.map({case (name, data) => s"${name}: ${data}"}).mkString(", ")}}" } diff --git a/sim/midas/src/main/scala/midas/core/SimWrapper.scala b/sim/midas/src/main/scala/midas/core/SimWrapper.scala index 7c103148..5eda14d2 100644 --- a/sim/midas/src/main/scala/midas/core/SimWrapper.scala +++ b/sim/midas/src/main/scala/midas/core/SimWrapper.scala @@ -3,7 +3,6 @@ package midas package core - import midas.widgets.BridgeIOAnnotation import midas.passes.fame import midas.passes.fame.{FAMEChannelConnectionAnnotation, DecoupledForwardChannel, FAMEChannelFanoutAnnotation} @@ -192,7 +191,6 @@ abstract class ChannelizedWrapperIO(val config: SimWrapperConfig) class ClockRecord(numClocks: Int) extends Record { override val elements = ListMap(Seq.tabulate(numClocks)(i => s"_$i" -> Clock()):_*) - override def cloneType = new ClockRecord(numClocks).asInstanceOf[this.type] } class TargetBoxIO(config: SimWrapperConfig) extends ChannelizedWrapperIO(config) { @@ -212,7 +210,6 @@ class TargetBoxIO(config: SimWrapperConfig) extends ChannelizedWrapperIO(config) override val elements = ListMap((Seq(clockElement) ++ wireElements ++ rvElements):_*) ++ // Untokenized ports ListMap("hostClock" -> hostClock, "hostReset" -> hostReset) - override def cloneType: this.type = new TargetBoxIO(config).asInstanceOf[this.type] } class TargetBox(config: SimWrapperConfig) extends BlackBox { @@ -229,7 +226,6 @@ class SimWrapperChannels(config: SimWrapperConfig) extends ChannelizedWrapperIO( }).get override val elements = ListMap((Seq(clockElement) ++ wireElements ++ rvElements):_*) - override def cloneType: this.type = new SimWrapperChannels(config).asInstanceOf[this.type] } /** diff --git a/sim/midas/src/main/scala/midas/models/dram/DramCommon.scala b/sim/midas/src/main/scala/midas/models/dram/DramCommon.scala index 1e6172fe..817df5ac 100644 --- a/sim/midas/src/main/scala/midas/models/dram/DramCommon.scala +++ b/sim/midas/src/main/scala/midas/models/dram/DramCommon.scala @@ -2,7 +2,6 @@ package midas package models import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.util.GenericParameterizedBundle import chisel3._ import chisel3.util._ @@ -345,7 +344,7 @@ class FirstReadyFCFSEntry(key: DRAMBaseConfig)(implicit p: Parameters) extends M // timing and resource constraints are met. The controller must also ensure CAS // commands use the open ROW. -class BankStateTrackerO(key: DramOrganizationParams) extends GenericParameterizedBundle(key) +class BankStateTrackerO(val key: DramOrganizationParams) extends Bundle with CommandLegalBools { import DRAMMasEnums._ @@ -355,7 +354,7 @@ class BankStateTrackerO(key: DramOrganizationParams) extends GenericParameterize def isRowHit(ref: MASEntry): Bool = ref.rowAddr === openRow && state === bank_active } -class BankStateTrackerIO(val key: DramOrganizationParams) extends GenericParameterizedBundle(key) +class BankStateTrackerIO(val key: DramOrganizationParams) extends Bundle with HasLegalityUpdateIO { val out = new BankStateTrackerO(key) val cmdUsesThisBank = Input(Bool()) @@ -443,7 +442,7 @@ class BankStateTracker(key: DramOrganizationParams) extends Module with HasDRAMM // timing and resource constraints are met. The controller must also ensure CAS // commands use the open ROW. -class RankStateTrackerO(key: DramOrganizationParams) extends GenericParameterizedBundle(key) +class RankStateTrackerO(val key: DramOrganizationParams) extends Bundle with CommandLegalBools { import DRAMMasEnums._ val canREF = Output(Bool()) @@ -452,7 +451,7 @@ class RankStateTrackerO(key: DramOrganizationParams) extends GenericParameterize val banks = Vec(key.maxBanks, Output(new BankStateTrackerO(key))) } -class RankStateTrackerIO(val key: DramOrganizationParams) extends GenericParameterizedBundle(key) +class RankStateTrackerIO(val key: DramOrganizationParams) extends Bundle with HasLegalityUpdateIO with HasDRAMMASConstants { val rank = new RankStateTrackerO(key) val tCycle = Input(UInt(maxDRAMTimingBits.W)) @@ -605,7 +604,7 @@ class CommandBusMonitor extends Module { } } -class RankRefreshUnitIO(key: DramOrganizationParams) extends GenericParameterizedBundle(key) { +class RankRefreshUnitIO(val key: DramOrganizationParams) extends Bundle { val rankStati = Vec(key.maxRanks, Flipped(new RankStateTrackerO(key))) // The user may have instantiated multiple ranks, but is only modelling a single // rank system. Don't issue refreshes to ranks we aren't modelling diff --git a/sim/midas/src/main/scala/midas/passes/AnnotationWiringTransform.scala b/sim/midas/src/main/scala/midas/passes/AnnotationWiringTransform.scala index a9f47860..6dce3e10 100644 --- a/sim/midas/src/main/scala/midas/passes/AnnotationWiringTransform.scala +++ b/sim/midas/src/main/scala/midas/passes/AnnotationWiringTransform.scala @@ -1,5 +1,5 @@ //See LICENSE for license details. -// + package midas.passes import midas.targetutils._ diff --git a/sim/midas/src/main/scala/midas/passes/EnsureNoTargetIO.scala b/sim/midas/src/main/scala/midas/passes/EnsureNoTargetIO.scala index 1448ee67..c3f55ce2 100644 --- a/sim/midas/src/main/scala/midas/passes/EnsureNoTargetIO.scala +++ b/sim/midas/src/main/scala/midas/passes/EnsureNoTargetIO.scala @@ -2,11 +2,9 @@ package midas.passes - import firrtl._ import firrtl.ir._ - // Ensures that there are no dangling IO on the target. All I/O coming off the DUT must be bound // to an Bridge BlackBox case class TargetMalformedException(message: String) extends RuntimeException(message) diff --git a/sim/midas/src/main/scala/midas/passes/HoistStopAndPrintfEnables.scala b/sim/midas/src/main/scala/midas/passes/HoistStopAndPrintfEnables.scala index b39b63a6..f9de83e3 100644 --- a/sim/midas/src/main/scala/midas/passes/HoistStopAndPrintfEnables.scala +++ b/sim/midas/src/main/scala/midas/passes/HoistStopAndPrintfEnables.scala @@ -1,4 +1,3 @@ - // See LICENSE for license details. package midas.passes diff --git a/sim/midas/src/main/scala/midas/passes/HostClockAnnotation.scala b/sim/midas/src/main/scala/midas/passes/HostClockAnnotation.scala index 7cc2a26d..510cc330 100644 --- a/sim/midas/src/main/scala/midas/passes/HostClockAnnotation.scala +++ b/sim/midas/src/main/scala/midas/passes/HostClockAnnotation.scala @@ -1,4 +1,5 @@ //See LICENSE for license details. + package midas.passes import firrtl.CircuitState diff --git a/sim/midas/src/main/scala/midas/passes/MidasTransforms.scala b/sim/midas/src/main/scala/midas/passes/MidasTransforms.scala index abcb2e1c..044f61e2 100644 --- a/sim/midas/src/main/scala/midas/passes/MidasTransforms.scala +++ b/sim/midas/src/main/scala/midas/passes/MidasTransforms.scala @@ -3,11 +3,8 @@ package midas package passes - - import firrtl._ - private[midas] class MidasTransforms extends Transform { def inputForm = LowForm def outputForm = HighForm diff --git a/sim/midas/src/main/scala/midas/passes/PrintSynthesis.scala b/sim/midas/src/main/scala/midas/passes/PrintSynthesis.scala index 3bad4e04..ae2dde96 100644 --- a/sim/midas/src/main/scala/midas/passes/PrintSynthesis.scala +++ b/sim/midas/src/main/scala/midas/passes/PrintSynthesis.scala @@ -9,7 +9,6 @@ import firrtl.ir._ import firrtl.Mappers._ import firrtl.Utils.{zero, BoolType} - import midas.passes.fame.{FAMEChannelConnectionAnnotation, WireChannel} import midas.widgets.{BridgeIOAnnotation, PrintBridgeModule, PrintBridgeParameters, PrintPort} import midas.targetutils.{SynthPrintfAnnotation, GlobalResetConditionSink} diff --git a/sim/midas/src/main/scala/midas/passes/SimulationMapping.scala b/sim/midas/src/main/scala/midas/passes/SimulationMapping.scala index 95210776..95959828 100644 --- a/sim/midas/src/main/scala/midas/passes/SimulationMapping.scala +++ b/sim/midas/src/main/scala/midas/passes/SimulationMapping.scala @@ -3,8 +3,6 @@ package midas package passes - - import firrtl._ import firrtl.annotations.{CircuitName, ModuleTarget, InstanceTarget} import firrtl.options.Dependency @@ -117,4 +115,3 @@ private[passes] class SimulationMapping(targetName: String) extends firrtl.Trans linkedState.copy(annotations = linkedState.annotations ++ generateHeaderAnnos(shim)) } } - diff --git a/sim/midas/src/main/scala/midas/passes/TargetClockAnalysis.scala b/sim/midas/src/main/scala/midas/passes/TargetClockAnalysis.scala index e6099692..278b4217 100644 --- a/sim/midas/src/main/scala/midas/passes/TargetClockAnalysis.scala +++ b/sim/midas/src/main/scala/midas/passes/TargetClockAnalysis.scala @@ -8,7 +8,6 @@ import midas.widgets.{RationalClock} import firrtl._ import firrtl.annotations._ - /** * [[ChannelClockInfoAnalysis]]'s output annotation. Maps channel global name * (See [[FAMEChannelConnectionAnnotation]] to a clock info class. diff --git a/sim/midas/src/main/scala/midas/passes/package.scala b/sim/midas/src/main/scala/midas/passes/package.scala index 14812261..de62ae2d 100644 --- a/sim/midas/src/main/scala/midas/passes/package.scala +++ b/sim/midas/src/main/scala/midas/passes/package.scala @@ -9,8 +9,6 @@ import annotations._ import firrtl.Utils.BoolType import firrtl.transforms.BlackBoxInlineAnno - - package object passes { /** * A utility for keeping statements defining and connecting signals to a piece of hardware @@ -34,9 +32,9 @@ package object passes { /** * This pass ensures that the AbstractClockGate blackbox is defined in a circuit, so that it can * later be instantiated. The blackbox clock gate has the following signature: - * + * * module AbstractClockGate(input I, input CE, output O); - * + * * I and O are the input and output clocks, respectively, while CE is the enable signal. */ object DefineAbstractClockGate extends Transform with FunctionalPass[CircuitName] { @@ -90,7 +88,7 @@ package object passes { /** * Transforms a partial function with matching input and output types into a total function. In * cases where the partial function is not defined, the identity function is used. - * + * * @tparam T The type for both the input and output of the partial function * @param f The partial function to transform * @return Returns a total function (T) => T @@ -155,7 +153,7 @@ package object passes { * Recursively replace expressions in a Statement tree according to a map. Since the keys are * of type WrappedExpression, the matching is based on "WrappedExpression equality," which * ignores metadata that may be present in the nodes, like info, type, or kind. - * + * * @param repls A map defining how each expression (in wrapped form) is replaced by a matching value, if any * @param s The input statement to transform * @return Returns a statement tree transformed by substitution according to the replacement map @@ -165,7 +163,7 @@ package object passes { /** * A pass that is described as a chain of pure function calls. - * + * * @tparam T The type of the analysis object returned by the analysis phase. */ trait FunctionalPass[T] { diff --git a/sim/midas/src/main/scala/midas/widgets/AssertBridge.scala b/sim/midas/src/main/scala/midas/widgets/AssertBridge.scala index a14a9c9d..d1f03145 100644 --- a/sim/midas/src/main/scala/midas/widgets/AssertBridge.scala +++ b/sim/midas/src/main/scala/midas/widgets/AssertBridge.scala @@ -14,7 +14,6 @@ class AssertBridgeRecord(assertPortName: String, resetPortName: String, numAsser val asserts = Output(UInt(numAsserts.W)) val underGlobalReset = Output(Bool()) val elements = ListMap(assertPortName -> asserts, resetPortName -> underGlobalReset) - override def cloneType = new AssertBridgeRecord(assertPortName, resetPortName, numAsserts).asInstanceOf[this.type] } case class AssertBridgeParameters(assertPortName: String, resetPortName: String, assertMessages: Seq[String]) diff --git a/sim/midas/src/main/scala/midas/widgets/AutoCounterBridge.scala b/sim/midas/src/main/scala/midas/widgets/AutoCounterBridge.scala index 3811af5b..950bbc0a 100644 --- a/sim/midas/src/main/scala/midas/widgets/AutoCounterBridge.scala +++ b/sim/midas/src/main/scala/midas/widgets/AutoCounterBridge.scala @@ -56,7 +56,6 @@ class AutoCounterBundle( (triggerName, triggerEnable) +: (resetPortName, underGlobalReset) +: events):_*) - override def cloneType = new AutoCounterBundle(eventMetadata, triggerName, resetPortName).asInstanceOf[this.type] } case class AutoCounterParameters(eventMetadata: Seq[EventMetadata], triggerName: String, resetPortName: String) diff --git a/sim/midas/src/main/scala/midas/widgets/HostPort.scala b/sim/midas/src/main/scala/midas/widgets/HostPort.scala index b8703a9c..0970dcbc 100644 --- a/sim/midas/src/main/scala/midas/widgets/HostPort.scala +++ b/sim/midas/src/main/scala/midas/widgets/HostPort.scala @@ -33,8 +33,6 @@ class HostPortIO[+T <: Data](private val targetPortProto: T) extends Record with val elements = collection.immutable.ListMap(Seq("fromHost" -> fromHost, "toHost" -> toHost, "hBits" -> hBits):_*) - override def cloneType: this.type = new HostPortIO(targetPortProto).asInstanceOf[this.type] - private[midas] def getClock(): Clock = { val allTargetClocks = SimUtils.findClocks(targetPortProto) require(allTargetClocks.nonEmpty, diff --git a/sim/midas/src/main/scala/midas/widgets/PeekPokeIO.scala b/sim/midas/src/main/scala/midas/widgets/PeekPokeIO.scala index 733074fb..ec3cbf3e 100644 --- a/sim/midas/src/main/scala/midas/widgets/PeekPokeIO.scala +++ b/sim/midas/src/main/scala/midas/widgets/PeekPokeIO.scala @@ -180,7 +180,6 @@ class PeekPokeTokenizedIO(private val targetIO: PeekPokeTargetIO) extends Record val outs = targetOutputs.map({ case (field, name) => name -> InputChannel(field) }) val ins = targetInputs.map({ case (field, name) => name -> OutputChannel(field) }) override val elements = ListMap((ins ++ outs):_*) - override def cloneType = new PeekPokeTokenizedIO(targetIO).asInstanceOf[this.type] } object PeekPokeTokenizedIO { @@ -210,7 +209,6 @@ class PeekPokeTargetIO(targetIO: Seq[(String, Data)]) extends Record { Seq("clock" -> clock) ++ targetIO.map({ case (name, field) => name -> Flipped(chiselTypeOf(field)) }) ):_*) - override def cloneType = new PeekPokeTargetIO(targetIO).asInstanceOf[this.type] } class PeekPokeBridge(targetIO: Seq[(String, Data)]) extends BlackBox diff --git a/sim/midas/src/main/scala/midas/widgets/PrintBridge.scala b/sim/midas/src/main/scala/midas/widgets/PrintBridge.scala index e7b2d05e..eb943b15 100644 --- a/sim/midas/src/main/scala/midas/widgets/PrintBridge.scala +++ b/sim/midas/src/main/scala/midas/widgets/PrintBridge.scala @@ -25,7 +25,6 @@ class PrintRecord(portType: firrtl.ir.BundleType, val formatString: String) exte val enable = Output(Bool()) val elements = ListMap((Seq("enable" -> enable) ++ args):_*) - override def cloneType = new PrintRecord(portType, formatString).asInstanceOf[this.type] // Gets the bit position of each argument after the record has been flattened to a UInt def argumentOffsets() = args.foldLeft(Seq(enable.getWidth))({ @@ -43,7 +42,6 @@ class PrintRecordBag(resetPortName: String, printPorts: Seq[(firrtl.ir.Port, Str }) val elements = ListMap(((resetPortName -> underGlobalReset) +: printRecords):_*) - override def cloneType = new PrintRecordBag(resetPortName, printPorts).asInstanceOf[this.type] // Generates a Bool indicating if at least one Printf has it's enable set on this cycle def hasEnabledPrint(): Bool = printRecords.map(_._2.enable).foldLeft(false.B)(_ || _) && !underGlobalReset diff --git a/sim/midas/src/main/scala/midas/widgets/SerializationUtils.scala b/sim/midas/src/main/scala/midas/widgets/SerializationUtils.scala index 0eeb1a1a..a19edb00 100644 --- a/sim/midas/src/main/scala/midas/widgets/SerializationUtils.scala +++ b/sim/midas/src/main/scala/midas/widgets/SerializationUtils.scala @@ -31,7 +31,6 @@ object SerializationUtils { val inputPorts = inputs.map(field => field.name -> Input(field.regenType())) val outputPorts = outputs.map(field => field.name -> Output(field.regenType())) override val elements = immutable.ListMap((inputPorts ++ outputPorts):_*) - override def cloneType = new RegeneratedTargetIO(inputs, outputs).asInstanceOf[this.type] } } diff --git a/sim/src/main/makefrag/bridges/driver.mk b/sim/src/main/makefrag/bridges/driver.mk index a6815233..bd1cf9b1 100644 --- a/sim/src/main/makefrag/bridges/driver.mk +++ b/sim/src/main/makefrag/bridges/driver.mk @@ -15,6 +15,7 @@ DRIVER_CC := \ $(driver_dir)/bridges/BridgeHarness.cc \ $(driver_dir)/bridges/$(DESIGN).cc \ $(testchipip_csrc_dir)/testchip_tsi.cc \ + $(testchipip_csrc_dir)/testchip_htif.cc \ $(wildcard $(addprefix $(firesim_lib_dir)/, \ bridges/uart.cc \ bridges/tsibridge.cc \ diff --git a/sim/src/main/makefrag/firesim/driver.mk b/sim/src/main/makefrag/firesim/driver.mk index 339a51c1..8faf50dc 100644 --- a/sim/src/main/makefrag/firesim/driver.mk +++ b/sim/src/main/makefrag/firesim/driver.mk @@ -43,14 +43,16 @@ DRIVER_H = \ $(shell find $(driver_dir) -name "*.h") \ $(shell find $(firesim_lib_dir) -name "*.h") \ $(DROMAJO_REQS) \ - $(TESTCHIPIP_CSRC_DIR)/testchip_tsi.h + $(TESTCHIPIP_CSRC_DIR)/testchip_tsi.h \ + $(TESTCHIPIP_CSRC_DIR)/testchip_htif.h DRIVER_CC = \ $(addprefix $(driver_dir)/firesim/, $(addsuffix .cc, firesim_top)) \ $(wildcard $(addprefix $(firesim_lib_dir)/, $(addsuffix .cc, bridges/* fesvr/* bridges/tracerv/*))) \ $(RISCV)/lib/libfesvr.a \ $(DROMAJO_LIB_DIR)/lib$(DROMAJO_LIB_NAME).a \ - $(TESTCHIPIP_CSRC_DIR)/testchip_tsi.cc + $(TESTCHIPIP_CSRC_DIR)/testchip_tsi.cc \ + $(TESTCHIPIP_CSRC_DIR)/testchip_htif.cc # Disable missing override warning for testchipip. TARGET_CXX_FLAGS += -g \ diff --git a/sim/src/main/scala/midasexamples/PointerChaser.scala b/sim/src/main/scala/midasexamples/PointerChaser.scala index f0d1adfd..d1431da5 100644 --- a/sim/src/main/scala/midasexamples/PointerChaser.scala +++ b/sim/src/main/scala/midasexamples/PointerChaser.scala @@ -60,7 +60,7 @@ class PointerChaserDUT(implicit val p: Parameters) extends Module with HasNastiP when (rFire && memoryIF.r.bits.last){ resultValid := isFinalNode - resultReg := resultReg + memoryIF.r.bits.data.asSInt() + resultReg := resultReg + memoryIF.r.bits.data.asSInt }.elsewhen (doneFire) { resultValid := false.B resultReg := 0.S diff --git a/target-design/chipyard b/target-design/chipyard index 336f2251..65ed3c16 160000 --- a/target-design/chipyard +++ b/target-design/chipyard @@ -1 +1 @@ -Subproject commit 336f225143590f9060ebe7101e96f235f96db985 +Subproject commit 65ed3c162cc3d57c19d19621803a830a5f867e97