2023-05-11 15:24:55 +08:00
|
|
|
<!--
|
2022-02-18 07:28:18 +08:00
|
|
|
First, please ensure that the title of your PR is sufficient to include in the next changelog.
|
|
|
|
|
Refer to https://github.com/firesim/firesim/releases for examples and feel free to ask reviewers for help.
|
|
|
|
|
|
|
|
|
|
Then, make sure to label your PR with one of the changelog:<section> labels to indicate which section
|
|
|
|
|
of the changelog should contain this PR's title:
|
|
|
|
|
changelog:added
|
|
|
|
|
changelog:changed
|
|
|
|
|
changelog:fixed
|
|
|
|
|
changelog:removed
|
|
|
|
|
|
|
|
|
|
If you feel that this PR should not be included in the changelog, you must still label it with
|
|
|
|
|
changelog:omit
|
|
|
|
|
|
|
|
|
|
Provide a brief description of the PR immediately below this comment, if the title is insufficient -->
|
2021-02-05 05:17:18 +08:00
|
|
|
|
|
|
|
|
#### Related PRs / Issues
|
|
|
|
|
|
|
|
|
|
<!-- List any related issues here -->
|
|
|
|
|
|
|
|
|
|
#### UI / API Impact
|
|
|
|
|
|
|
|
|
|
<!-- Roughly, how would this affect the current API or user-facing interfaces? (extend, deprecate, remove, or break) -->
|
2023-05-11 15:24:55 +08:00
|
|
|
<!-- Of note: manager config_*.yaml interface, targetutils & bridge scala API, platform config behavior -->
|
2021-02-05 05:17:18 +08:00
|
|
|
|
2021-06-16 07:03:09 +08:00
|
|
|
#### Verilog / AGFI Compatibility
|
2021-02-05 05:17:18 +08:00
|
|
|
|
|
|
|
|
<!-- Does this change the generated Verilog or the simulator memory map of the default targets? -->
|
|
|
|
|
|
|
|
|
|
### Contributor Checklist
|
2022-02-18 07:28:18 +08:00
|
|
|
- [ ] Is this PR's title suitable for inclusion in the changelog and have you added a `changelog:<topic>` label?
|
|
|
|
|
- [ ] Did you add Scaladoc/docstring/doxygen to every public function/method?
|
2021-02-05 05:17:18 +08:00
|
|
|
- [ ] Did you add at least one test demonstrating the PR?
|
|
|
|
|
- [ ] Did you delete any extraneous prints/debugging code?
|
|
|
|
|
- [ ] Did you state the UI / API impact?
|
2021-06-16 07:03:09 +08:00
|
|
|
- [ ] Did you specify the Verilog / AGFI compatibility impact?
|
2021-02-05 05:17:18 +08:00
|
|
|
<!-- Do this if this PR changes verilog or breaks the default AGFIs -->
|
2022-02-23 06:41:02 +08:00
|
|
|
- [ ] If applicable, did you regenerate and publicly share default AGFIs?
|
|
|
|
|
<!--
|
|
|
|
|
CI will check linux boot on default targets, when the <ci:fpga-deploy> label is applied. Do this on:
|
|
|
|
|
- Chipyard bumps / AGFIs updates / RTL or Driver changes affecting default targets.
|
|
|
|
|
- If in doubt request a deployment, or ask another developer.
|
|
|
|
|
|
|
|
|
|
NB: This *label* should be applied before the PR is created, or the branch
|
|
|
|
|
will need to be resychronized to trigger a new CI workflow with the FPGA-deployment jobs.
|
|
|
|
|
-->
|
|
|
|
|
- [ ] If applicable, did you apply the `ci:fpga-deploy` label?
|
2022-02-18 07:28:18 +08:00
|
|
|
<!-- Do this if this PR is a bugfix that should be applied to the latest release -->
|
2022-02-23 06:41:02 +08:00
|
|
|
- [ ] If applicable, did you apply the `Please Backport` label?
|
2021-02-05 05:17:18 +08:00
|
|
|
|
|
|
|
|
### Reviewer Checklist (only modified by reviewer)
|
2022-08-13 07:18:38 +08:00
|
|
|
Note: to run CI on PRs from forks, comment `@Mergifyio copy main` and manage the change from the new PR.
|
2022-02-18 07:28:18 +08:00
|
|
|
- [ ] Is the title suitable for inclusion in the changelog and does the PR have a `changelog:<topic>` label?
|
2021-06-16 07:03:09 +08:00
|
|
|
- [ ] Did you mark the proper release milestone?
|
2021-02-05 05:17:18 +08:00
|
|
|
- [ ] Did you check whether all relevant Contributor checkboxes have been checked?
|
