Daniel Kroening b9dc889f1f Verilog: function/task ports ... This adds support for port declarations as part of the function/task header.		2024-02-05 06:15:04 -08:00
..
Array1	use new test.pl script	2015-12-05 13:49:33 +00:00
Memory1	ebmc: revise property status output	2023-12-06 11:56:24 -08:00
Memory2	ebmc: revise property status output	2023-12-06 11:56:24 -08:00
arbiter1	ebmc: revise property status output	2023-12-06 11:56:24 -08:00
arrays	Verilog: implement System Verilog arrays with size	2023-12-19 13:34:57 -08:00
assert1	ebmc: revise property status output	2023-12-06 11:56:24 -08:00
assert2	ebmc: revise property status output	2023-12-06 11:56:24 -08:00
assignment-to-concatenation	CI: run the Verilog tests with Z3	2024-02-03 08:22:27 -08:00
assignment-to-range1	CI: run the Verilog tests with Z3	2024-02-03 08:22:27 -08:00
assignment-with-function-call	this is a bug	2016-11-23 18:26:07 +00:00
bit-extract	CI: run the Verilog tests with Z3	2024-02-03 08:22:27 -08:00
case	CI: run the Verilog tests with Z3	2024-02-03 08:22:27 -08:00
casts	Verilog: System Verilog typecasts	2023-12-15 08:30:53 -08:00
class	Verilog: System Verilog classes	2023-12-15 16:24:01 -08:00
comments	Verilog: allow EOF in single line comments	2023-11-01 14:26:41 -07:00
concatenation	Verilog: enable simplification of concatenations with signed operands	2023-12-18 14:42:06 -08:00
constants1	update expected outputs	2016-01-04 14:03:26 +00:00
data-types	Verilog: add tests for combiations of declarations	2024-02-01 11:47:43 -08:00
delays	Verilog: support time literals	2023-11-29 12:08:36 -08:00
elaboration	Verilog: elaborate wire symbols	2024-02-01 11:01:20 -08:00
for	Verilog: propagate constants of any type during synthesis	2023-12-08 06:33:25 -08:00
functioncall	Verilog: function/task ports	2024-02-05 06:15:04 -08:00
generate	CI: run the Verilog tests with Z3	2024-02-03 08:22:27 -08:00
generate1	CI: run the Verilog tests with Z3	2024-02-03 08:22:27 -08:00
hierarchical_identifiers	Verilog: fix nested hierarchical identifiers	2023-12-05 17:00:39 -08:00
hierarchy1	update expected outputs	2016-01-04 14:03:26 +00:00
indexed-part-select1	CI: run the Verilog tests with Z3	2024-02-03 08:22:27 -08:00
initial1	update expected outputs	2016-01-04 14:03:26 +00:00
modules	CI: run the Verilog tests with Z3	2024-02-03 08:22:27 -08:00
multiple_assign1	CI: run the Verilog tests with Z3	2024-02-03 08:22:27 -08:00
named_blocks1	update expected outputs	2016-01-04 14:03:26 +00:00
nondet1	CI: run the Verilog tests with Z3	2024-02-03 08:22:27 -08:00
operators1	test two bits	2016-04-02 19:24:43 +00:00
package	Verilog: System Verilog packages	2023-12-16 17:08:30 -08:00
preprocessor	Verilog: --preprocess now honors -I	2024-01-03 15:23:34 +00:00
primitive_gates	update expected outputs	2016-01-04 14:03:26 +00:00
replication	Verilog: replication count may be zero	2024-02-03 08:32:13 -08:00
sensitivity_list1	update expected outputs	2016-01-04 14:03:26 +00:00
shr1	update expected outputs	2016-01-04 14:03:26 +00:00
signed1	update expected outputs	2016-01-04 14:03:26 +00:00
string	Verilog: fix string literals	2023-12-10 07:06:11 -08:00
synthesis	Verilog: Add a KNOWNBUG test for a crash	2023-12-04 13:45:24 -08:00
system-functions	ebmc: revise property status output	2023-12-06 11:56:24 -08:00
system_verilog_assertion	CI: run the Verilog tests with Z3	2024-02-03 08:22:27 -08:00
system_verilog_types1	more tests	2017-07-04 17:47:00 +01:00
tasks	Verilog: add source location for function/task symbols	2024-02-01 13:15:54 -08:00
typedef	Verilog: clean up base_name vs identifier in declarators	2024-02-04 12:49:18 -08:00
Makefile	CI: run the Verilog tests with Z3	2024-02-03 08:22:27 -08:00