Verilog: add source location for function/task symbols

regression/verilog/tasks/task_name_collision.desc

@@ -1,9 +1,8 @@
-KNOWNBUG
+CORE
 task_name_collision.v
 
-^definition of symbol `some_task' conflicts with earlier definition at line$
+^file .* line 11: definition of symbol `some_task' conflicts with earlier definition at line 7$
 ^EXIT=2$
 ^SIGNAL=0$
 --
 --
-The line number is missing.

src/verilog/verilog_elaborate.cpp

@@ -523,6 +523,7 @@ void verilog_typecheckt::collect_symbols(const verilog_declt &decl)
     symbolt symbol{identifier, code_typet{{}, std::move(return_type)}, mode};
 
     symbol.base_name = base_name;
+    symbol.location = decl.source_location();
     symbol.pretty_name = strip_verilog_prefix(symbol.name);
     symbol.module = module_identifier;
     symbol.value = decl;