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print synthesis module name

This commit is contained in:
Daniel Kroening 2013-04-29 18:06:47 +00:00
parent 66824fe2b1
commit 2fc56474a7
1 changed files with 1 additions and 1 deletions
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src/verilog/verilog_language.cpp
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@ -165,7 +165,7 @@ bool verilog_languaget::typecheck(
if(verilog_typecheck(parse_tree, symbol_table, module, message_handler))
return true;
message_handler.print(9, "Synthesis");
message_handler.print(9, "Synthesis "+module);
if(verilog_synthesis(symbol_table, module, message_handler, options))
return true;