From 2fc56474a71cfe1736b4a91d18d76475dc4c50f9 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <kroening@cs.ox.ac.uk>
Date: Mon, 29 Apr 2013 18:06:47 +0000
Subject: [PATCH] print synthesis module name

---
 src/verilog/verilog_language.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/verilog/verilog_language.cpp b/src/verilog/verilog_language.cpp
index 1fdd307..d357d97 100644
--- a/src/verilog/verilog_language.cpp
+++ b/src/verilog/verilog_language.cpp
@@ -165,7 +165,7 @@ bool verilog_languaget::typecheck(
   if(verilog_typecheck(parse_tree, symbol_table, module, message_handler))
     return true;
     
-  message_handler.print(9, "Synthesis");
+  message_handler.print(9, "Synthesis "+module);
 
   if(verilog_synthesis(symbol_table, module, message_handler, options))
     return true;