Overview

A framework for dual-output LUT mapping.

How To Use

Compilation

make

Execution

./bin/dom <benchamrk-set> <benchmark-name>

Example:

./bin/dom EPFL adder

Interpretation of the Results

*.blif_abc_lut.blif.out is the result from berkeley-abc.

*.blif.out1 is the single-output result.

*.blif.out2 is the dual-output result.

Reference

@inproceedings{wang2020dom,
  title={Dual-Output LUT Merging during FPGA Technology Mapping},
  author={Wang, Feng and Zhu, Liren and Zhang, Jiaxi and Li, Lei and Zhang, Yang and Luo, Guojie},
  booktitle={Proceedings of the 39th International Conference on Computer-Aided Design},
  pages={1--9},
  year={2020},
}