pulled out clocking and started source dirs. files from internal private repos

common/rocketchip_wrapper.v

@@ -1,4 +1,5 @@
 `timescale 1 ps / 1 ps
+`include "clocking.vh"
 
 module zed_refchip_wrapper
    (DDR_addr,
@@ -502,16 +503,16 @@ module zed_refchip_wrapper
 
   MMCME2_BASE #(
     .BANDWIDTH("OPTIMIZED"),
-    .CLKFBOUT_MULT_F(8.0),
+    .CLKFBOUT_MULT_F(`RC_CLK_MULT),
     .CLKFBOUT_PHASE(0.0),
-    .CLKIN1_PERIOD(10.0),
+    .CLKIN1_PERIOD(`ZYNQ_CLK_PERIOD),
     .CLKOUT1_DIVIDE(1),
     .CLKOUT2_DIVIDE(1),
     .CLKOUT3_DIVIDE(1),
     .CLKOUT4_DIVIDE(1),
     .CLKOUT5_DIVIDE(1),
     .CLKOUT6_DIVIDE(1),
-    .CLKOUT0_DIVIDE_F(10.0),
+    .CLKOUT0_DIVIDE_F(`RC_CLK_DIVIDE),
     .CLKOUT0_DUTY_CYCLE(0.5),
     .CLKOUT1_DUTY_CYCLE(0.5),
     .CLKOUT2_DUTY_CYCLE(0.5),

zedboard/hw/src/verilog/clocking.vh

@@ -0,0 +1,33 @@
+/*
+
+Rocket Chip Clock Configuration
+
+
+Rocket Chip             1000              RC_CLK_MULT
+ Clockrate     =   ---------------   X   -------------
+  (in MHz)         ZYNQ_CLK_PERIOD       RC_CLK_DIVIDE
+
+
+This sets the parameters used by rocketchip_wrapper.v to
+generate its own clock.
+
+Most uses should only change RC_CLK_MULT & RC_CLK_DIVIDE.
+ZYNQ_CLK_PERIOD should only be changed to match the input
+clock period set in the Vivado GUI and 
+hw/src/constrs/pin_constraints.xdc
+
+*/
+
+
+`ifndef _clocking_vh_
+`define _clocking_vh_
+
+
+`define ZYNQ_CLK_PERIOD 10.0
+
+`define RC_CLK_MULT     10.0
+
+`define RC_CLK_DIVIDE   40.0
+
+
+`endif // _clocking_vh_

zedboard/rtl

@@ -0,0 +1 @@
+hw/src/verilog

zybo/hw/src/verilog/clocking.vh

@@ -0,0 +1,33 @@
+/*
+
+Rocket Chip Clock Configuration
+
+
+Rocket Chip             1000              RC_CLK_MULT
+ Clockrate     =   ---------------   X   -------------
+  (in MHz)         ZYNQ_CLK_PERIOD       RC_CLK_DIVIDE
+
+
+This sets the parameters used by rocketchip_wrapper.v to
+generate its own clock.
+
+Most uses should only change RC_CLK_MULT & RC_CLK_DIVIDE.
+ZYNQ_CLK_PERIOD should only be changed to match the input
+clock period set in the Vivado GUI and 
+hw/src/constrs/pin_constraints.xdc
+
+*/
+
+
+`ifndef _clocking_vh_
+`define _clocking_vh_
+
+
+`define ZYNQ_CLK_PERIOD  8.0
+
+`define RC_CLK_MULT      8.0
+
+`define RC_CLK_DIVIDE   40.0
+
+
+`endif // _clocking_vh_

zybo/rtl

@@ -0,0 +1 @@
+hw/src/verilog