From d287a91e5b438308ee764f8749cd4dd00eca2bb0 Mon Sep 17 00:00:00 2001 From: Scott Beamer Date: Wed, 10 Sep 2014 14:57:08 -0700 Subject: [PATCH] pulled out clocking and started source dirs. files from internal private repos --- common/rocketchip_wrapper.v | 7 +++--- zedboard/hw/src/verilog/clocking.vh | 33 +++++++++++++++++++++++++++++ zedboard/rtl | 1 + zybo/hw/src/verilog/clocking.vh | 33 +++++++++++++++++++++++++++++ zybo/rtl | 1 + 5 files changed, 72 insertions(+), 3 deletions(-) create mode 100644 zedboard/hw/src/verilog/clocking.vh create mode 120000 zedboard/rtl create mode 100644 zybo/hw/src/verilog/clocking.vh create mode 120000 zybo/rtl diff --git a/common/rocketchip_wrapper.v b/common/rocketchip_wrapper.v index 3525b72..d1d0aaa 100644 --- a/common/rocketchip_wrapper.v +++ b/common/rocketchip_wrapper.v @@ -1,4 +1,5 @@ `timescale 1 ps / 1 ps +`include "clocking.vh" module zed_refchip_wrapper (DDR_addr, @@ -502,16 +503,16 @@ module zed_refchip_wrapper MMCME2_BASE #( .BANDWIDTH("OPTIMIZED"), - .CLKFBOUT_MULT_F(8.0), + .CLKFBOUT_MULT_F(`RC_CLK_MULT), .CLKFBOUT_PHASE(0.0), - .CLKIN1_PERIOD(10.0), + .CLKIN1_PERIOD(`ZYNQ_CLK_PERIOD), .CLKOUT1_DIVIDE(1), .CLKOUT2_DIVIDE(1), .CLKOUT3_DIVIDE(1), .CLKOUT4_DIVIDE(1), .CLKOUT5_DIVIDE(1), .CLKOUT6_DIVIDE(1), - .CLKOUT0_DIVIDE_F(10.0), + .CLKOUT0_DIVIDE_F(`RC_CLK_DIVIDE), .CLKOUT0_DUTY_CYCLE(0.5), .CLKOUT1_DUTY_CYCLE(0.5), .CLKOUT2_DUTY_CYCLE(0.5), diff --git a/zedboard/hw/src/verilog/clocking.vh b/zedboard/hw/src/verilog/clocking.vh new file mode 100644 index 0000000..de81968 --- /dev/null +++ b/zedboard/hw/src/verilog/clocking.vh @@ -0,0 +1,33 @@ +/* + +Rocket Chip Clock Configuration + + +Rocket Chip 1000 RC_CLK_MULT + Clockrate = --------------- X ------------- + (in MHz) ZYNQ_CLK_PERIOD RC_CLK_DIVIDE + + +This sets the parameters used by rocketchip_wrapper.v to +generate its own clock. + +Most uses should only change RC_CLK_MULT & RC_CLK_DIVIDE. +ZYNQ_CLK_PERIOD should only be changed to match the input +clock period set in the Vivado GUI and +hw/src/constrs/pin_constraints.xdc + +*/ + + +`ifndef _clocking_vh_ +`define _clocking_vh_ + + +`define ZYNQ_CLK_PERIOD 10.0 + +`define RC_CLK_MULT 10.0 + +`define RC_CLK_DIVIDE 40.0 + + +`endif // _clocking_vh_ diff --git a/zedboard/rtl b/zedboard/rtl new file mode 120000 index 0000000..921e52c --- /dev/null +++ b/zedboard/rtl @@ -0,0 +1 @@ +hw/src/verilog \ No newline at end of file diff --git a/zybo/hw/src/verilog/clocking.vh b/zybo/hw/src/verilog/clocking.vh new file mode 100644 index 0000000..d487d7e --- /dev/null +++ b/zybo/hw/src/verilog/clocking.vh @@ -0,0 +1,33 @@ +/* + +Rocket Chip Clock Configuration + + +Rocket Chip 1000 RC_CLK_MULT + Clockrate = --------------- X ------------- + (in MHz) ZYNQ_CLK_PERIOD RC_CLK_DIVIDE + + +This sets the parameters used by rocketchip_wrapper.v to +generate its own clock. + +Most uses should only change RC_CLK_MULT & RC_CLK_DIVIDE. +ZYNQ_CLK_PERIOD should only be changed to match the input +clock period set in the Vivado GUI and +hw/src/constrs/pin_constraints.xdc + +*/ + + +`ifndef _clocking_vh_ +`define _clocking_vh_ + + +`define ZYNQ_CLK_PERIOD 8.0 + +`define RC_CLK_MULT 8.0 + +`define RC_CLK_DIVIDE 40.0 + + +`endif // _clocking_vh_ diff --git a/zybo/rtl b/zybo/rtl new file mode 120000 index 0000000..921e52c --- /dev/null +++ b/zybo/rtl @@ -0,0 +1 @@ +hw/src/verilog \ No newline at end of file