Go to file
Guojie Luo a7645b2e10 Support replication expressions 2023-04-24 12:41:44 +00:00
src Support replication expressions 2023-04-24 12:41:44 +00:00
test add parameter verilog case 2022-07-19 20:15:56 +08:00
.gitignore Create a preliminary codegen from CST to LLHD 2022-02-12 21:09:47 +08:00
Cargo.lock Support high-impedance numbers and inout port 2022-05-24 14:26:52 +08:00
Cargo.toml Support high-impedance numbers and inout port 2022-05-24 14:26:52 +08:00
LICENSE Add license file 2022-03-25 23:35:04 +08:00
README.md Add license file 2022-03-25 23:35:04 +08:00

README.md

cst-to-llhd

cst-to-llhd: Convert a Verible concrete syntax tree (CST) to an LLHD graph.

USAGE:
    cst-to-llhd <input>

FLAGS:
    -h, --help       Prints help information
    -V, --version    Prints version information

ARGS:
    <input>    CST file in JSON format

sv-to-llhd

sv-to-llhd: Convert a Verilog file to LLHD.

USAGE:
    sv-to-llhd <input>

FLAGS:
    -h, --help       Prints help information
    -V, --version    Prints version information

ARGS:
    <input>    the Verilog file to convert

Dependencies