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add parameter verilog case

This commit is contained in:
Yanting Zhang 2022-07-19 20:15:56 +08:00
parent 624f80ad72
commit 473e7e49eb
2 changed files with 1331 additions and 0 deletions
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1312
test/addition.json Normal file
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19
test/addition.v Normal file
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@ -0,0 +1,19 @@
module addition
#(
parameter DSIZE = 8
)
(
input [DSIZE-1:0] a,
input [DSIZE-1:0] b,
output [DSIZE-1:0] c
);
assign c = a + b;
endmodule
module top(
input [3:0] a,
input [3:0] b,
output [3:0] c
);
addition#(.DSIZE(4)) i(a, b, c);
endmodule