 Guojie Luo
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9682ad0340
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Add UnitData in ModuleContext/UnitContext
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2022-03-18 19:34:03 +08:00 |
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Guojie Luo
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80dc88afee
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Add preliminary codegen for event expression list
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2022-03-18 08:45:13 +08:00 |
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Guojie Luo
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779405b22e
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Maintain sensitive list
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2022-03-16 21:10:26 +08:00 |
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Guojie Luo
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e8a6fedc99
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Remove a variable in ModuleContext
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2022-03-16 19:53:39 +08:00 |
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Guojie Luo
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be64cf9b03
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Add a few instructions for the always statement
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2022-03-07 22:26:03 +08:00 |
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Guojie Luo
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dbecb9889f
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Make minor modifications
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2022-02-27 20:48:09 +08:00 |
张燕婷2001210542
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2e49adf424
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update tag.rs
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2022-02-27 19:19:36 +08:00 |
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张燕婷2001210542
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ed5e74e695
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update verilog-2005
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2022-02-27 19:16:39 +08:00 |
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Guojie Luo
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deb3ee2b23
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Remove HashSet::from(...)
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2022-02-27 11:20:21 +08:00 |
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Guojie Luo
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47d2307d1f
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Reorganize code for port & reg declaration
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2022-02-27 10:43:02 +08:00 |
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Guojie Luo
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66cfb51cab
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Support process instantiation
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2022-02-27 02:20:09 +08:00 |
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Guojie Luo
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d172cbe5dd
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Add CaseStatement and NetVariableAssignment
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2022-02-26 23:49:22 +08:00 |
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Guojie Luo
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429703ab70
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Support parameter declaration
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2022-02-26 17:53:13 +08:00 |
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Guojie Luo
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2f7a073c3a
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Support wire declaration
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2022-02-26 16:48:03 +08:00 |
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Guojie Luo
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56747f67a4
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Import input/output port extraction
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2022-02-26 16:04:24 +08:00 |
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Guojie Luo
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f3265cf832
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Improve process instantiation
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2022-02-26 13:53:11 +08:00 |
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Guojie Luo
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f828f4177d
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Add EventExpressionList
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2022-02-26 00:36:42 +08:00 |
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Guojie Luo
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84f1d283ed
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Keep track of r-values when visiting expressions
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2022-02-26 00:16:43 +08:00 |
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Guojie Luo
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6974551843
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Build and instantiate processes
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2022-02-25 22:47:49 +08:00 |
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Guojie Luo
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e46dbbcd7c
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Work on a correct instantiation of ExtUnit
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2022-02-25 21:30:15 +08:00 |
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Guojie Luo
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b0ffc2cfaa
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Make minor updates
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2022-02-25 14:11:24 +08:00 |
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Guojie Luo
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5284760090
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Make minor updates
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2022-02-24 10:07:54 +08:00 |
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Guojie Luo
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975d44e212
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Add more placeholders with TODO messages
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2022-02-24 09:13:15 +08:00 |
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Guojie Luo
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c93df679d3
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Add empty methods to go through "fpga_hdl_defect/"
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2022-02-24 08:19:27 +08:00 |
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Guojie Luo
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403d0d3112
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Add cst::ProceduralTimingControlStatement
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2022-02-21 23:18:34 +08:00 |
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Guojie Luo
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cda478df3e
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Update executable x-lint
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2022-02-19 17:43:44 +08:00 |
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Guojie Luo
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43ce73e5e2
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Add executable x-lint
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2022-02-19 15:29:58 +08:00 |
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Guojie Luo
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d3c4fbc626
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Update cst::AlwaysStatement
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2022-02-19 12:50:51 +08:00 |
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Guojie Luo
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dda95883e4
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Add cst::AlwaysStatement
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2022-02-19 10:41:17 +08:00 |
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Guojie Luo
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1f827c176f
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Add ModuleContext
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2022-02-15 21:57:53 +08:00 |
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Guojie Luo
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92c19776cc
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Add one more test case
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2022-02-14 22:00:45 +08:00 |
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Guojie Luo
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427b47d602
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Improve the parsing of I/O ports
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2022-02-14 20:04:27 +08:00 |
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Guojie Luo
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2bb1ff9f45
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Create a preliminary codegen from CST to LLHD
TO-DO
* add a Context class to decouple the node analyzers
* learn codegen implementation from verible, moore, etc.
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2022-02-12 21:09:47 +08:00 |
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Guojie Luo
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5be44ad94f
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Initial commit
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2022-02-11 16:53:53 +08:00 |