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Jiawei Lin ffc9cee438
Merge pull request #13 from hyf6661669/main 
添加说明文档
 		2022-01-13 20:27:52 +08:00
fpdiv_scalar Fix typo 2022-01-11 19:15:23 +08:00
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README.md Update README.md 2021-07-01 12:25:04 +08:00

README.md

XS-Verilog-Library

如果你对香山处理器感兴趣，希望参与到香山处理器的开发中，但又对Chisel/Scala不熟悉，那么你可以使用Verilog/System Verilog进行开发，并在本仓库中提出Pull Request，熟悉Chisel和Scala的开发者会将你的代码用Chisel重写并merge到香山中，重写的Chisel代码中会保留你的姓名，并会附上一个指向你在本仓库中代码的链接。