set alias bits in sourceB mask
This commit is contained in:
parent
5701abe374
commit
e9671666c0
|
@ -39,6 +39,7 @@ class SourceBReq(implicit p: Parameters) extends HuanCunBundle {
|
|||
val tag = UInt(tagBits.W)
|
||||
val param = UInt(3.W)
|
||||
val clients = UInt(clientBits.W)
|
||||
val alias = aliasBitsOpt.map(w => UInt(w.W))
|
||||
}
|
||||
class SinkCReq(implicit p: Parameters) extends InnerTask {
|
||||
val size = UInt(msgSizeBits.W)
|
||||
|
|
|
@ -187,6 +187,7 @@ class HuanCun(implicit p: Parameters) extends LazyModule with HasHuanCunParamete
|
|||
val inclusion = if (cacheParams.inclusive) "Inclusive" else "Non-inclusive"
|
||||
val prefetch = "prefetch: " + cacheParams.prefetch.nonEmpty
|
||||
println(s"====== ${inclusion} ${cacheParams.name} ($sizeStr) $prefetch ======")
|
||||
aliasBitsOpt.foreach(bits => println(s"aliasBits: $bits"))
|
||||
node.in.zip(node.out).foreach {
|
||||
case ((in, edgeIn), (out, edgeOut)) =>
|
||||
require(in.params.dataBits == out.params.dataBits)
|
||||
|
|
|
@ -54,7 +54,7 @@ class SourceB(implicit p: Parameters) extends HuanCunModule {
|
|||
io.b.bits.size := offsetBits.U
|
||||
io.b.bits.source := getSourceId(chosenClient)
|
||||
io.b.bits.address := Cat(taskLatch.tag, taskLatch.set, 0.U(offsetBits.W))
|
||||
io.b.bits.mask := ~0.U(beatBytes.W)
|
||||
io.b.bits.mask := taskLatch.alias.getOrElse(0.U)
|
||||
io.b.bits.data := 0.U
|
||||
io.b.bits.corrupt := 0.U
|
||||
}
|
||||
|
|
|
@ -29,7 +29,7 @@ class SelfDirEntry(implicit p: Parameters) extends HuanCunBundle {
|
|||
|
||||
class ClientDirEntry(implicit p: Parameters) extends HuanCunBundle {
|
||||
val state = UInt(stateBits.W)
|
||||
val alias = aliasBitsOpt.map(_ => UInt(aliasBitsOpt.get.W))
|
||||
val alias = aliasBitsOpt.map(bits => UInt(bits.W))
|
||||
}
|
||||
|
||||
class SelfDirResult(implicit p: Parameters) extends SelfDirEntry {
|
||||
|
|
|
@ -662,15 +662,8 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S
|
|||
),
|
||||
io.dirResult.valid
|
||||
)
|
||||
ob.set := {
|
||||
if (!hasAliasBits) req.set
|
||||
else
|
||||
Cat(
|
||||
req.set.head(setBits - log2Ceil(clientCacheParams.sets)),
|
||||
probe_alias,
|
||||
req.set(clientSetBits - 1, 0)
|
||||
)
|
||||
}
|
||||
ob.set := req.set
|
||||
ob.alias.foreach(_ := probe_alias)
|
||||
assert(ob.set.getWidth == req.set.getWidth)
|
||||
ob.param := Mux(
|
||||
req.fromB,
|
||||
|
|
Loading…
Reference in New Issue