MSHRAlloc: avoid dead lock
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@ -61,8 +61,6 @@ class MSHRAlloc(implicit p: Parameters) extends HuanCunModule {
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/* Select one request from a_req/b_req/c_req */
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/* Select one request from a_req/b_req/c_req */
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val request = Wire(ValidIO(new MSHRRequest()))
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val request = Wire(ValidIO(new MSHRRequest()))
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request.valid := io.c_req.valid || io.b_req.valid || io.a_req.valid
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request.bits := Mux(io.c_req.valid, io.c_req.bits, Mux(io.b_req.valid, io.b_req.bits, io.a_req.bits))
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/* Whether selected request can be accepted */
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/* Whether selected request can be accepted */
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@ -113,13 +111,20 @@ class MSHRAlloc(implicit p: Parameters) extends HuanCunModule {
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val mshrFree = Cat(abc_mshr_status.map(s => !s.valid)).orR()
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val mshrFree = Cat(abc_mshr_status.map(s => !s.valid)).orR()
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val can_accept_c = (mshrFree && !conflict_c) || nestC
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val can_accept_c = (mshrFree && !conflict_c) || nestC
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val can_accept_b = ((mshrFree && !conflict_b) || nestB) && !io.c_req.valid
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val can_accept_a = mshrFree && !conflict_a && !io.c_req.valid && !io.b_req.valid
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val accept_c = io.c_req.valid && can_accept_c
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val accept_c = io.c_req.valid && can_accept_c
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val can_accept_b = ((mshrFree && !conflict_b) || nestB) && !accept_c
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val accept_b = io.b_req.valid && can_accept_b
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val accept_b = io.b_req.valid && can_accept_b
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val can_accept_a = mshrFree && !conflict_a && !io.c_req.valid && !io.b_req.valid
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val accept_a = io.a_req.valid && can_accept_a
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val accept_a = io.a_req.valid && can_accept_a
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request.valid := io.c_req.valid || io.b_req.valid || io.a_req.valid
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request.bits := Mux(accept_c,
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io.c_req.bits,
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Mux(io.b_req.valid, io.b_req.bits, io.a_req.bits)
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)
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/* Provide signals for outer components*/
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/* Provide signals for outer components*/
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io.c_req.ready := dirRead.ready && can_accept_c
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io.c_req.ready := dirRead.ready && can_accept_c
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io.b_req.ready := dirRead.ready && can_accept_b
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io.b_req.ready := dirRead.ready && can_accept_b
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@ -139,13 +144,13 @@ class MSHRAlloc(implicit p: Parameters) extends HuanCunModule {
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mshr.bits := request.bits
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mshr.bits := request.bits
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}
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}
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val nestB_valid = io.b_req.valid && nestB && !io.c_req.valid
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val nestB_valid = io.b_req.valid && nestB && !accept_c
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val nestC_valid = io.c_req.valid && nestC
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val nestC_valid = io.c_req.valid && nestC
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bc_mshr_alloc.valid := nestB_valid && dirRead.ready
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bc_mshr_alloc.valid := nestB_valid && dirRead.ready
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bc_mshr_alloc.bits := request.bits
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bc_mshr_alloc.bits := io.b_req.bits
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c_mshr_alloc.valid := nestC_valid && dirRead.ready
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c_mshr_alloc.valid := nestC_valid && dirRead.ready
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c_mshr_alloc.bits := request.bits
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c_mshr_alloc.bits := io.c_req.bits
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dirRead.valid := request.valid && Cat(accept_c, accept_b, accept_a).orR() && dirRead.ready
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dirRead.valid := request.valid && Cat(accept_c, accept_b, accept_a).orR() && dirRead.ready
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dirRead.bits.source := request.bits.source
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dirRead.bits.source := request.bits.source
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