Merge pull request #42 from OpenXiangShan/perf-counter

disable performance counter name print logic

src/main/scala/huancun/HuanCun.scala

@@ -71,6 +71,7 @@ trait HasHuanCunParameters {
   val numPCntHcReqb   = 6
   val numPCntHcProb   = 1
   val numPCntHc       = numPCntHcMSHR + numPCntHcDir + numPCntHcReqb + numPCntHcProb
+  val print_hcperfcounter  = false
 
   lazy val edgeIn = p(EdgeInKey)
   lazy val edgeOut = p(EdgeOutKey)

src/main/scala/huancun/MSHRAlloc.scala

@@ -218,6 +218,6 @@ class MSHRAlloc(implicit p: Parameters) extends HuanCunModule {
   )
 
   for (((perf_out,(perf_name,perf)),i) <- perfinfo.zip(perfEvents).zipWithIndex) {
-    perf_out := perf
+    perf_out := RegNext(perf)
   }
 }

src/main/scala/huancun/RequestBuffer.scala

@@ -113,6 +113,6 @@ class RequestBuffer(flow: Boolean = true, entries: Int = 16)(implicit p: Paramet
   )
 
   for (((perf_out,(perf_name,perf)),i) <- perfinfo.zip(perfEvents).zipWithIndex) {
-    perf_out := perf
+    perf_out := RegNext(perf)
   }
 }

src/main/scala/huancun/Slice.scala

@@ -578,6 +578,8 @@ class Slice()(implicit p: Parameters) extends HuanCunModule {
   val perfinfo = IO(Output(Vec(numPCntHc, (UInt(6.W)))))
   for (((perf_out,(perf_name,perf)),i) <- perfinfo.zip(huancun_perf).zipWithIndex) {
     perf_out := perf
-    println(s"frontend perf $i: $perf_name")
+    if(print_hcperfcounter){
+      println(s"Huancun perf $i: $perf_name")
+    }
   }
 }

src/main/scala/huancun/noninclusive/Directory.scala

@@ -342,6 +342,6 @@ class Directory(implicit p: Parameters)
   )
 
   for (((perf_out,(perf_name,perf)),i) <- perfinfo.zip(perfEvents).zipWithIndex) {
-    perf_out := perf
+    perf_out := RegNext(perf)
   }
 }

src/main/scala/huancun/noninclusive/ProbeHelper.scala

@@ -67,6 +67,6 @@ class ProbeHelper(entries: Int = 4, enqDelay: Int = 1)(implicit p: Parameters)
   )
 
   for (((perf_out,(perf_name,perf)),i) <- perfinfo.zip(perfEvents).zipWithIndex) {
-    perf_out := perf
+    perf_out := RegNext(perf)
   }
 }