61a8ccef44
boot: sanity check for SMP lock variable state
65fa542b2a
boot: declare variable just for the loop
321bc31e4a
trivial: Improve formatting in isMDBParentOf
45bf84798c
arm,smc: Handle revoke cap operations
d9b868238a
arm,smc: follow syscall message passing convention
2134cc09b3
Update BibTeX
1dc2748c20
Additional changes to seeding
39d0ef4386
Make seeding more consistent
410e182902
Fix another seeding bug
451642c8f3
Fix seeding bug
da5d0e7d30
Fixes for multimer config features and cropping
3de188e9d0
Minor model test fix
a18f98cf25
Seed fixes for multimer data pipeline
44b0bf76d0
Merge branch 'main' into multimer
1dc2748c20
Additional changes to seeding
1eb0beafa5
[ci] Consolidate Verible linting workflow into one stage
06df66452f
[credits] Add names of recent contributors
8dd8d52241
print period and budget with units
aa118c25b8
use types time_t and tickts_t properly
cbad541120
doc: improve comments
0792eebc0a
Fix enabling of AArch64 user-level cache ops
1ca227a1b5
boot: simplify boot code recycling
8332aa0e88
Merge pull request #331 from dingquanyu/multimer
85693530c3
update compute_tm so that it accomodates batch_size dimension in the input data
56d5e39cb6
Merge remote-tracking branch 'upstream/multimer' into multimer
56b86074bf
Merge pull request #1 from aqlaboratory/main
55003f1676
Fix batched finetuning bugs
f60d03b6b0
Update google_riscv-dv to chipsalliance/riscv-dv@08b1206
44ed214caa
[vendor] Use new RISCV-DV URL
18c6053fcf
[dv,doc] Point reference to lowRISC branch
e791ed49f3
Update riscv-isa-sim to lowrisc/riscv-isa-sim@a4b823a1
5a485db97b
Update riscv-isa-sim to lowrisc/riscv-isa-sim@a7c5d5d8
1d878a1203
Fix assert bug
7fdb503e76
Fix evoformer test
d5da89c13e
Fix model test
df06706528
Fix utils tests
7139313ad3
[vendor] Minor alignment improvement
d33fc90375
[dv] Move DVSIM data structures
a1d5d49d10
[dv] Add common_ifs_pkg.sv to DV files
2b1e3de746
Update lowrisc_ip to lowRISC/opentitan@0deeaa99e
bfe2c2f3c0
[vendor] Patch updated based on OpenTitan/36a2d3c
2e47ccd632
GEN: Updated interface specification.
80cf2d2a17
ARM: Initialize interrupts and scheduling.
e5533fac12
ARM: Unified PD,EC,SC,PT,SM,HIP,MBUF class.
33f6645939
ARM: Added SMMU.
ce73540dce
ARM: Added HIP.
zxs-un
synced commits to refs/tags/release-23.26.0 at secc/NOVA-microhypervisor from mirror
2023-07-11 14:04:24 +08:00
zxs-un
synced new reference refs/tags/release-23.26.0 to secc/NOVA-microhypervisor from mirror
2023-07-11 14:04:24 +08:00
zxs-un
synced commits to gh-readonly-queue/master/pr-2051-90ee203a9a44773061e824711d281d2c3557a200 at secc/ibex from mirror
2023-06-23 21:50:42 +08:00
zxs-un
synced new reference gh-readonly-queue/master/pr-2051-90ee203a9a44773061e824711d281d2c3557a200 to secc/ibex from mirror
2023-06-23 21:50:42 +08:00
fbd070cf58
[dv] New directed test to cover some scenarios with U-mode execution
4e17587213
[dv] Fix SET_PMP_CFG macro used by directed tests
a7845832a2
[dv,fcov] Add additional illegal bins to PMP fcov
4fe6d89ed3
[dv, fcov] Increase iterations of riscv_mem_intg_error_test
49f4ddfc8c
SMP: Fixup compilation error
3c180701ee
remove Arch_migrateTCB()
7354779dde
remove obsolete assert()
147e291fe2
trivial: fix typos
2730e65796
Mark CLINT as reserved device on RISC-V platforms