229 lines
7.1 KiB
Plaintext
229 lines
7.1 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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comment "ARMV8M Configuration Options"
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config ARMV8M_HAVE_ICACHE
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bool
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default n
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config ARMV8M_HAVE_DCACHE
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bool
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default n
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config ARMV8M_LAZYFPU
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bool "Lazy FPU storage"
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default n
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depends on ARCH_HAVE_LAZYFPU
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---help---
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There are two forms of the common vector logic. There are pros and
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cons to each option:
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1) The standard common vector logic exploits features of the ARMv8-M
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architecture to save the all of floating registers on entry into
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each interrupt and then to restore the floating registers when
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the interrupt returns. The primary advantage to this approach is
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that floating point operations are available in interrupt
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handling logic. Since the volatile registers are preserved,
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operations on the floating point registers by interrupt handling
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logic has no ill effect. The downside is, of course, that more
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stack operations are required on each interrupt to save and store
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the floating point registers. Because of the some special
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features of the ARMv-M, this is not as much overhead as you might
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expect, but overhead nonetheless.
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2) The lazy FPU common vector logic does not save or restore
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floating point registers on entry and exit from the interrupt
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handler. Rather, the floating point registers are not restored
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until it is absolutely necessary to do so when a context switch
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occurs and the interrupt handler will be returning to a different
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floating point context. Since floating point registers are not
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protected, floating point operations must not be performed in
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interrupt handling logic. Better interrupt performance is be
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expected, however.
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By default, the "standard" common vector logic is build. This
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option selects the alternate lazy FPU common vector logic.
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config ARMV8M_USEBASEPRI
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bool "Use BASEPRI Register"
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default y if ARCH_HIPRI_INTERRUPT
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---help---
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Use the BASEPRI register to enable and disable interrupts. By
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default, the PRIMASK register is used for this purpose. This
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usually results in hardfaults when supervisor calls are made.
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Though, these hardfaults are properly handled by the RTOS, the
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hardfaults can confuse some debuggers. With the BASEPRI
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register, these hardfaults, will be avoided. For more details see
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https://cwiki.apache.org/confluence/display/NUTTX/ARMv7-M+Hardfaults%2C+SVCALL%2C+and+Debuggers
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WARNING: If CONFIG_ARCH_HIPRI_INTERRUPT is selected, then you
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MUST select CONFIG_ARMV8M_USEBASEPRI. The Kconfig dependencies
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here will permit to select an invalid configuration because it
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cannot enforce that requirement. If you create this invalild
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configuration, you will encounter some problems that may be
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very difficult to debug.
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config ARMV8M_ICACHE
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bool "Use I-Cache"
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default n
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depends on ARMV8M_HAVE_ICACHE
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select ARCH_ICACHE
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config ARMV8M_DCACHE
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bool "Use D-Cache"
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default n
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depends on ARMV8M_HAVE_DCACHE
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select ARCH_DCACHE
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config ARMV8M_DCACHE_WRITETHROUGH
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bool "D-Cache Write-Through"
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default n
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depends on ARMV8M_DCACHE
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config ARMV8M_HAVE_ITCM
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bool
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default n
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config ARMV8M_HAVE_DTCM
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bool
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default n
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config ARMV8M_ITCM
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bool "Use ITCM"
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default n
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depends on ARMV8M_HAVE_ITCM
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config ARMV8M_DTCM
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bool "Use DTCM"
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default n
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depends on ARMV8M_HAVE_DTCM
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choice
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prompt "Toolchain Selection"
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default ARMV8M_TOOLCHAIN_GNU_EABIW if TOOLCHAIN_WINDOWS
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default ARMV8M_TOOLCHAIN_GNU_EABIL if !TOOLCHAIN_WINDOWS
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config ARMV8M_TOOLCHAIN_BUILDROOT
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bool "Buildroot (Cygwin or Linux)"
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depends on !WINDOWS_NATIVE
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select ARCH_TOOLCHAIN_GNU
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config ARMV8M_TOOLCHAIN_GNU_EABIL
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bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
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depends on !WINDOWS_NATIVE
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select ARCH_TOOLCHAIN_GNU
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---help---
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This option should work for any modern GNU toolchain (GCC 4.5 or newer)
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configured for arm-none-eabi.
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config ARMV8M_TOOLCHAIN_GNU_EABIW
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bool "Generic GNU EABI toolchain under Windows"
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depends on TOOLCHAIN_WINDOWS
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select CYGWIN_WINTOOL if WINDOWS_CYGWIN
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select ARCH_TOOLCHAIN_GNU
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config ARMV8M_TOOLCHAIN_CLANGL
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bool "Generic Clang toolchain under Linux (or other POSIX environment)"
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depends on !WINDOWS_NATIVE
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select ARCH_TOOLCHAIN_GNU
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config ARMV8M_TOOLCHAIN_CLANGW
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bool "Generic Clang toolchain under Windows"
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depends on TOOLCHAIN_WINDOWS
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select CYGWIN_WINTOOL if WINDOWS_CYGWIN
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select ARCH_TOOLCHAIN_GNU
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---help---
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This option should work for any modern GNU toolchain (GCC 4.5 or newer)
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configured for arm-none-eabi.
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endchoice
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config ARMV8M_OABI_TOOLCHAIN
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bool "OABI (vs EABI)"
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default n
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depends on ARMV8M_TOOLCHAIN_BUILDROOT
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---help---
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Most of the older buildroot toolchains are OABI and are named
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arm-nuttx-elf- vs. arm-nuttx-eabi-
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config ARMV8M_TARGET2_PREL
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bool "R_ARM_TARGET2 is PC relative"
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default n if !CXX_EXCEPTION
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default y if CXX_EXCEPTION
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depends on LIBC_ARCH_ELF
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---help---
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Perform a PC relative relocation for relocation type R_ARM_TARGET2
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choice
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prompt "Select the stack protection Schema"
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default ARMV8M_STACKCHECK_NONE
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config ARMV8M_STACKCHECK_NONE
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bool "Do not check for stack overflow"
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config ARMV8M_STACKCHECK
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bool "Check for stack overflow on each function call"
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---help---
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This check uses R10 to check for a stack overflow within each
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function call. This has performances and code size impacts, but it
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will be able to catch hard to find stack overflows.
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Currently only available only for the STM32, SAM3/4 and SAMA5D
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architectures. The changes are not complex and patches for
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other architectures will be accepted.
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This option requires that you are using a GCC toolchain and that
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you also include -finstrument-functions in your CFLAGS when you
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compile. This addition to your CFLAGS should probably be added
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to the definition of the CFFLAGS in your board Make.defs file.
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config ARMV8M_STACKCHECK_HARDWARE
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bool "Check for stack overflow by stack pointer limit register"
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---help---
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This option signifies the CPU has the MSPLIM, PSPLIM registers.
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The stack pointer limit registers, MSPLIM, PSPLIM, limit the
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extend to which the Main and Process Stack Pointers, respectively,
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can descend. MSPLIM, PSPLIM are always present in ARMv8-M
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MCUs that implement the ARMv8-M Main Extension (Mainline).
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In an ARMv8-M Mainline implementation with the Security Extension
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the MSPLIM, PSPLIM registers have additional Secure instances.
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In an ARMv8-M Baseline implementation with the Security Extension
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the MSPLIM, PSPLIM registers have only Secure instances.
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endchoice
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config ARMV8M_ITMSYSLOG
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bool "ITM SYSLOG support"
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default n
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select ARCH_SYSLOG
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select SYSLOG
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---help---
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Enable hooks to support ITM syslog output. This requires additional
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MCU support in order to be used. See arch/arm/src/armv8-m/itm_syslog.h
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for additional initialization information.
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if ARMV8M_ITMSYSLOG
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config ARMV8M_ITMSYSLOG_PORT
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int "ITM SYSLOG Port"
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default 0
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range 0 31
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config ARMV8M_ITMSYSLOG_SWODIV
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int "ITM SYSLOG SWO divider"
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default 15
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range 1 8192
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endif # ARMV8M_ITMSYSLOG
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config ARMV8M_SYSTICK
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bool "SysTick timer driver"
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depends on TIMER
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---help---
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Enable SysTick timer driver.
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