QEMU support for XiUOS based on Cortex-M3 from Hang_Yuqing
it is perfect
This commit is contained in:
commit
b318eb315c
2
Makefile
2
Makefile
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@ -5,7 +5,7 @@ MAKEFLAGS += --no-print-directory
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.PHONY:COMPILE_APP COMPILE_KERNEL
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support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator
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support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator
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SRC_DIR:=
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export BOARD ?=kd233
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@ -1,4 +1,12 @@
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#公共部分
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SRC_DIR := shared cortex-m4
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SRC_DIR := shared
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ifeq ($(CONFIG_BOARD_CORTEX_M3_EVB),y)
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SRC_DIR +=cortex-m3
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endif
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ifeq ($(CONFIG_BOARD_STM32F407_EVB),y)
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SRC_DIR +=cortex-m4
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endif
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include $(KERNEL_ROOT)/compiler.mk
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@ -0,0 +1,3 @@
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SRC_FILES := boot.c interrupt.c interrupt_vector.S
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include $(KERNEL_ROOT)/compiler.mk
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@ -0,0 +1,28 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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#ifndef ARCH_INTERRUPT_H__
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#define ARCH_INTERRUPT_H__
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#include <xs_base.h>
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#define ARCH_MAX_IRQ_NUM (256)
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#define ARCH_IRQ_NUM_OFFSET 0
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#define SYSTICK_IRQN 15
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#define UART1_IRQn 21
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int32 ArchEnableHwIrq(uint32 irq_num);
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int32 ArchDisableHwIrq(uint32 irq_num);
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#endif
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@ -0,0 +1,97 @@
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//*****************************************************************************
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//
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// startup_gcc.c - Startup code for use with GNU tools.
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//
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// Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved.
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||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
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||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 10636 of the Stellaris Firmware Development Package.
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//
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//*****************************************************************************
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/**
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* @file boot.c
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* @brief derived from Stellaris Firmware Development Package
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2021-05-13
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*/
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/*************************************************
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File name: boot.c
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Description: Reset and init function
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Others:
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History:
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1. Date: 2021-05-13
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Author: AIIT XUOS Lab
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Modification:
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1. take startup_gcc.c from revision 10636 of the Stellaris Firmware Development Package for XiUOS
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*************************************************/
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extern unsigned long _sidata;
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extern unsigned long _sdata;
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extern unsigned long _edata;
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extern unsigned long _sbss;
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extern unsigned long _ebss;
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extern int entry(void);
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void
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Reset_Handler(void)
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{
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unsigned long *pulSrc, *pulDest;
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//
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// Copy the data segment initializers from flash to SRAM.
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//
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pulSrc = &_sidata;
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for(pulDest = &_sdata; pulDest < &_edata; )
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{
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*pulDest++ = *pulSrc++;
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}
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//
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// Zero fill the bss segment.
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//
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__asm(" ldr r0, =_sbss\n"
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" ldr r1, =_ebss\n"
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" mov r2, #0\n"
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" .thumb_func\n"
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"zero_loop:\n"
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" cmp r0, r1\n"
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" it lt\n"
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" strlt r2, [r0], #4\n"
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" blt zero_loop");
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//
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// Call the application's entry point.
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//
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entry();
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}
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@ -0,0 +1,84 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
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*/
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/**
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* @file interrupt.c
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* @brief support arm cortex-m4 interrupt function
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2021-04-29
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*/
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#include <xs_base.h>
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#include <xs_isr.h>
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x_base __attribute__((naked)) DisableLocalInterrupt()
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{
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asm volatile ("MRS r0, PRIMASK");
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asm volatile ("CPSID I");
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asm volatile ("BX LR ");
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}
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void __attribute__((naked)) EnableLocalInterrupt(x_base level)
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{
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asm volatile ("MSR PRIMASK, r0");
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asm volatile ("BX LR");
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}
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int32 ArchEnableHwIrq(uint32 irq_num)
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{
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return EOK;
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}
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int32 ArchDisableHwIrq(uint32 irq_num)
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{
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return EOK;
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}
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extern void KTaskOsAssignAfterIrq(void *context);
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void IsrEntry()
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{
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uint32 ipsr;
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__asm__ volatile("MRS %0, IPSR" : "=r"(ipsr));
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isrManager.done->incCounter();
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isrManager.done->handleIrq(ipsr);
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KTaskOsAssignAfterIrq(NONE);
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isrManager.done->decCounter();
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}
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void UsageFault_Handler(int irqn, void *arg)
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{
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/* Go to infinite loop when Usage Fault exception occurs */
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while (1)
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{
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}
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}
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void BusFault_Handler(int irqn, void *arg)
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{
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/* Go to infinite loop when Bus Fault exception occurs */
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while (1)
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{
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}
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}
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void NMI_Handler(int irqn, void *arg)
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{
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while (1)
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{
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}
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}
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@ -0,0 +1,138 @@
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//*****************************************************************************
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||||
//
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||||
// startup_gcc.c - Startup code for use with GNU tools.
|
||||
//
|
||||
// Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 10636 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
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/**
|
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* @file interrupt_vector.S
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||||
* @brief derived from Stellaris Firmware Development Package
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-13
|
||||
*/
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||||
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/*************************************************
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File name: interrupt_vector.S
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Description: vector table for a Cortex M3
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Others:
|
||||
History:
|
||||
1. Date: 2021-05-13
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. take startup_gcc.c from revision 10636 of the Stellaris Firmware Development Package for XiUOS
|
||||
*************************************************/
|
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//*****************************************************************************
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//
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// The vector table. Note that the proper constructs must be placed on this to
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// ensure that it ends up at physical address 0x0000.0000.
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//
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//*****************************************************************************
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.globl InterruptVectors
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/******************************************************************************
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*******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type InterruptVectors, %object
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.size InterruptVectors, .-InterruptVectors
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InterruptVectors:
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.word _sp
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.word Reset_Handler
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.word NMI_Handler //NMI_Handler
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.word HardFaultHandler
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.word MemFaultHandler //MemManage_Handler
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.word BusFault_Handler //BusFault_Handler
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.word UsageFault_Handler //UsageFault_Handler
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.word IsrEntry
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.word IsrEntry
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.word IsrEntry
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.word IsrEntry
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.word IsrEntry //SVC_Handler
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.word IsrEntry //DebugMon_Handler
|
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.word IsrEntry
|
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.word PendSV_Handler
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.word IsrEntry //systick
|
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.word IsrEntry // GPIO Port A
|
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.word IsrEntry // GPIO Port B
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.word IsrEntry // GPIO Port C
|
||||
.word IsrEntry // GPIO Port D
|
||||
.word IsrEntry // GPIO Port E
|
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.word IsrEntry // UART0 Rx and Tx
|
||||
.word IsrEntry // UART1 Rx and Tx
|
||||
.word IsrEntry // SSI Rx and Tx
|
||||
.word IsrEntry // I2C Master and Slave
|
||||
.word IsrEntry // PWM Fault
|
||||
.word IsrEntry // PWM Generator 0
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.word IsrEntry // PWM Generator 1
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.word IsrEntry // PWM Generator 2
|
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.word IsrEntry // Quadrature Encoder
|
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.word IsrEntry // ADC Sequence 0
|
||||
.word IsrEntry // ADC Sequence 1
|
||||
.word IsrEntry // ADC Sequence 2
|
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.word IsrEntry // ADC Sequence 3
|
||||
.word IsrEntry // Watchdog timer
|
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.word IsrEntry // Timer 0 subtimer A
|
||||
.word IsrEntry // Timer 0 subtimer B
|
||||
.word IsrEntry // Timer 1 subtimer A
|
||||
.word IsrEntry // Timer 1 subtimer B
|
||||
.word IsrEntry // Timer 2 subtimer A
|
||||
.word IsrEntry // Timer 2 subtimer B
|
||||
.word IsrEntry // Analog Comparator 0
|
||||
.word IsrEntry // Analog Comparator 1
|
||||
.word IsrEntry // Analog Comparator 2
|
||||
.word IsrEntry // System Control (PLL, OSC,
|
||||
.word IsrEntry // FLASH Control
|
||||
.word IsrEntry // GPIO Port F
|
||||
.word IsrEntry // GPIO Port G
|
||||
.word IsrEntry // GPIO Port H
|
||||
.word IsrEntry // UART2 Rx and Tx
|
||||
.word IsrEntry // SSI1 Rx and Tx
|
||||
.word IsrEntry // Timer 3 subtimer A
|
||||
.word IsrEntry // Timer 3 subtimer B
|
||||
.word IsrEntry // I2C1 Master and Slave
|
||||
.word IsrEntry // Quadrature Encoder 1
|
||||
.word IsrEntry // CAN0
|
||||
.word IsrEntry // CAN1
|
||||
.word IsrEntry // CAN2
|
||||
.word IsrEntry // Ethernet
|
||||
.word IsrEntry // Hibernate
|
||||
.word IsrEntry // USB0
|
||||
.word IsrEntry // PWM Generator 3
|
||||
.word IsrEntry // uDMA Software Transfer
|
||||
.word IsrEntry // uDMA Error
|
||||
|
|
@ -14,7 +14,6 @@
|
|||
#include <xs_ktask.h>
|
||||
#include <xs_assign.h>
|
||||
#include "svc_handle.h"
|
||||
#include "stm32f4xx.h"
|
||||
#include <board.h>
|
||||
#include <shell.h>
|
||||
|
||||
|
|
@ -380,12 +379,6 @@ void MemFaultExceptionPrint(struct ExceptionInfo *ExceptionInfo)
|
|||
if ((ExceptionInfo->ExcReturn & 0x10) == 0)
|
||||
KPrintf("FPU active!\r\n");
|
||||
|
||||
KPrintf("CFSR: 0x%08x \n", (*((volatile unsigned long *)(SCB->CFSR))) );
|
||||
KPrintf("HFSR: 0x%08x \n", (*((volatile unsigned long *)(SCB->HFSR))) );
|
||||
KPrintf("DFSR: 0x%08x \n",(*((volatile unsigned long *)(SCB->DFSR))) );
|
||||
KPrintf("MMFAR: 0x%08x \n",(*((volatile unsigned long *)(SCB->MMFAR))));
|
||||
KPrintf("BFAR: 0x%08x \n",(*((volatile unsigned long *)(SCB->BFAR))));
|
||||
KPrintf("AFSR: 0x%08x \n",(*((volatile unsigned long *)(SCB->AFSR))));
|
||||
|
||||
#ifdef TOOL_SHELL
|
||||
HardFaultTrack();
|
||||
|
|
|
|||
|
|
@ -0,0 +1,248 @@
|
|||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# XiUOS Project Configuration
|
||||
#
|
||||
CONFIG_BOARD_CORTEX_M3_EVB=y
|
||||
CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uart0"
|
||||
#CONFIG_LED0=24
|
||||
#CONFIG_LED1=25
|
||||
CONFIG_ARCH_RISCV=y
|
||||
CONFIG_ARCH_RISCV32=y
|
||||
CONFIG_ARCH_CPU_32BIT=y
|
||||
|
||||
#
|
||||
# cortex-m3-emulator feature
|
||||
#
|
||||
# CONFIG_BSP_USING_AUDIO is not set
|
||||
# CONFIG_BSP_USING_CAMERA is not set
|
||||
# CONFIG_BSP_USING_SDIO is not set
|
||||
# CONFIG_BSP_USING_DMA is not set
|
||||
CONFIG_BSP_USING_GPIO=y
|
||||
# CONFIG_BSP_USING_I2C is not set
|
||||
# CONFIG_BSP_USING_I2S is not set
|
||||
# CONFIG_BSP_USING_LCD is not set
|
||||
# CONFIG_BSP_USING_RTC is not set
|
||||
# CONFIG_BSP_USING_SECURITY is not set
|
||||
# CONFIG_BSP_USING_SPI is not set
|
||||
CONFIG_BSP_USING_UART=y
|
||||
# CONFIG_BSP_USING_UART_HS is not set
|
||||
# CONFIG_BSP_USING_VIDEO is not set
|
||||
# CONFIG_BSP_USING_WDT is not set
|
||||
|
||||
#
|
||||
# General Purpose UARTs
|
||||
#
|
||||
|
||||
CONFIG___STACKSIZE__=4096
|
||||
|
||||
#
|
||||
# Hardware feature
|
||||
#
|
||||
CONFIG_RESOURCES_SERIAL=y
|
||||
# CONFIG_SERIAL_USING_DMA=y
|
||||
CONFIG_SERIAL_RB_BUFSZ=64
|
||||
CONFIG_FS_VFS=n
|
||||
# CONFIG_RESOURCES_HWTIMER is not set
|
||||
# CONFIG_RESOURCES_I2C is not set
|
||||
# CONFIG_RESOURCES_LCD is not set
|
||||
# CONFIG_RESOURCES_SDIO is not set
|
||||
# CONFIG_RESOURCES_TOUCH is not set
|
||||
# CONFIG_RESOURCES_PIN=y
|
||||
# CONFIG_RESOURCES_RTC is not set
|
||||
# CONFIG_RESOURCES_SPI is not set
|
||||
#CONFIG_RESOURCES_SPI_SD is not set
|
||||
#CONFIG_RESOURCES_SPI_SFUD is not set
|
||||
# SFUD_USING_SFDP is not set
|
||||
# SFUD_USING_FLASH_INFO_TABLE is not set
|
||||
# SFUD_DEBUG_LOG is not set
|
||||
# CONFIG_RESOURCES_WDT is not set
|
||||
# CONFIG_RESOURCES_USB is not set
|
||||
# CONFIG_RESOURCES_USB_HOST is not set
|
||||
# CONFIG_UDISK_MOUNTPOINT is not set
|
||||
# CONFIG_USBH_MSTORAGE is not set
|
||||
# CONFIG_RESOURCES_USB_DEVICE is not set
|
||||
# CONFIG_USBD_THREAD_STACK_SZ is not set
|
||||
|
||||
#
|
||||
# Kernel feature
|
||||
#
|
||||
|
||||
#
|
||||
# Kernel Device Object
|
||||
#
|
||||
CONFIG_KERNEL_DEVICE=y
|
||||
CONFIG_KERNEL_CONSOLE=y
|
||||
CONFIG_KERNEL_CONSOLEBUF_SIZE=128
|
||||
|
||||
#
|
||||
# Task feature
|
||||
#
|
||||
CONFIG_SCHED_POLICY_RR_REMAINSLICE=y
|
||||
# CONFIG_SCHED_POLICY_RR is not set
|
||||
# CONFIG_SCHED_POLICY_FIFO is not set
|
||||
|
||||
#
|
||||
# Memory Management
|
||||
#
|
||||
# CONFIG_KERNEL_MEMBLOCK is not set
|
||||
CONFIG_MEM_ALIGN_SIZE=4
|
||||
CONFIG_MM_PAGE_SIZE=1024
|
||||
|
||||
#
|
||||
# Using small memory allocator
|
||||
#
|
||||
CONFIG_KERNEL_SMALL_MEM_ALLOC=y
|
||||
CONFIG_SMALL_NUMBER_32B=32
|
||||
CONFIG_SMALL_NUMBER_64B=16
|
||||
|
||||
#
|
||||
# Inter-Task communication
|
||||
#
|
||||
# CONFIG_KERNEL_SEMAPHORE=y
|
||||
# CONFIG_KERNEL_MUTEX=y
|
||||
CONFIG_KERNEL_EVENT=n
|
||||
CONFIG_KERNEL_MESSAGEQUEUE=n
|
||||
CONFIG_KTASK_PRIORITY_8=y
|
||||
CONFIG_KTASK_PRIORITY_MAX=8
|
||||
CONFIG_TICK_PER_SECOND=100
|
||||
# CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y
|
||||
CONFIG_KERNEL_BANNER=y
|
||||
# CONFIG_KERNEL_HOOK is not set
|
||||
# CONFIG_KERNEL_SOFTTIMER=y
|
||||
# CONFIG_KERNEL_IDLE_HOOK=y
|
||||
# CONFIG_IDEL_HOOK_LIST_SIZE=4
|
||||
CONFIG_IDLE_KTASK_STACKSIZE=512
|
||||
CONFIG_ZOMBIE_KTASK_STACKSIZE=512
|
||||
# CONFIG_KERNEL_TASK_ISOLATION is not set
|
||||
|
||||
#
|
||||
# Memory Management
|
||||
#
|
||||
# CONFIG_KERNEL_MEMBLOCK is not set
|
||||
|
||||
#
|
||||
# Command shell
|
||||
#
|
||||
CONFIG_TOOL_SHELL=y
|
||||
CONFIG_SHELL_TASK_PRIORITY=4
|
||||
CONFIG_SHELL_TASK_STACK_SIZE=2048
|
||||
|
||||
#
|
||||
# User Control
|
||||
#
|
||||
CONFIG_SHELL_DEFAULT_USER="letter"
|
||||
CONFIG_SHELL_DEFAULT_USER_PASSWORD=""
|
||||
CONFIG_SHELL_LOCK_TIMEOUT=10000
|
||||
CONFIG_SHELL_ENTER_CR_AND_LF=y
|
||||
# CONFIG_SHELL_ENTER_CRLF is not set
|
||||
CONFIG_SHELL_ENTER_CR=y
|
||||
CONFIG_SHELL_ENTER_LF=y
|
||||
CONFIG_SHELL_MAX_NUMBER=5
|
||||
CONFIG_SHELL_PARAMETER_MAX_NUMBER=8
|
||||
CONFIG_SHELL_HISTORY_MAX_NUMBER=5
|
||||
CONFIG_SHELL_PRINT_BUFFER=128
|
||||
CONFIG_SHELL_USING_CMD_EXPORT=y
|
||||
# CONFIG_SHELL_HELP_LIST_USER is not set
|
||||
CONFIG_SHELL_HELP_SHOW_PERMISSION=y
|
||||
# CONFIG_SHELL_HELP_LIST_VAR is not set
|
||||
# CONFIG_SHELL_HELP_LIST_KEY is not set
|
||||
#CONFIG_KERNEL_QUEUEMANAGE=y
|
||||
# CONFIG_KERNEL_WORKQUEUE is not set
|
||||
CONFIG_WORKQUEUE_KTASK_STACKSIZE=256
|
||||
CONFIG_WORKQUEUE_KTASK_PRIORITY=2
|
||||
CONFIG_QUEUE_MAX=2
|
||||
CONFIG_KERNEL_WAITQUEUE=y
|
||||
CONFIG_KERNEL_DATAQUEUE=y
|
||||
# CONFIG_KERNEL_CIRCULAR_AREA is not set
|
||||
# CONFIG_KERNEL_AVL_TREE is not set
|
||||
CONFIG_NAME_MAX=32
|
||||
CONFIG_ALIGN_SIZE=8
|
||||
CONFIG_KERNEL_COMPONENTS_INIT=n
|
||||
CONFIG_KERNEL_USER_MAIN=y
|
||||
CONFIG_MAIN_KTASK_STACK_SIZE=2048
|
||||
CONFIG_ENV_INIT_KTASK_STACK_SIZE=2048
|
||||
CONFIG_MAIN_KTASK_PRIORITY=3
|
||||
# CONFIG_USER_TEST is not set
|
||||
# CONFIG_TOOL_TEST_SEM is not set
|
||||
# CONFIG_TOOL_TEST_MUTEX is not set
|
||||
# CONFIG_TOOL_TEST_EVENT is not set
|
||||
# CONFIG_TOOL_TEST_MSG is not set
|
||||
# CONFIG_TOOL_TEST_AVLTREE is not set
|
||||
# CONFIG_TEST_CRICULAR_AREA is not set
|
||||
# CONFIG_TOOL_TEST_MEM is not set
|
||||
# CONFIG_TOOL_TEST_TIMER is not set
|
||||
# CONFIG_TOOL_TEST_IWG is not set
|
||||
# CONFIG_TOOL_TEST_REALTIME is not set
|
||||
# CONFIG_TOOL_TEST_DBG is not set
|
||||
# CONFIG_TOOL_TEST_SCHED is not set
|
||||
# CONFIG_KERNEL_DEBUG is not set
|
||||
#CONFIG_DEBUG_INIT_CONFIG=y
|
||||
#CONFIG_DBG_INIT=1
|
||||
#CONFIG_ARCH_SMP=y
|
||||
#CONFIG_CPUS_NR=2
|
||||
|
||||
#
|
||||
# hash table config
|
||||
#
|
||||
CONFIG_ID_HTABLE_SIZE=4
|
||||
CONFIG_ID_NUM_MAX=16
|
||||
|
||||
#
|
||||
# File system
|
||||
#
|
||||
CONFIG_FS_DFS=n
|
||||
#CONFIG_DFS_USING_WORKDIR=y
|
||||
#CONFIG_FS_DFS_DEVFS=y
|
||||
|
||||
#
|
||||
# Fat filesystem
|
||||
#
|
||||
|
||||
#
|
||||
# IOT-Device File system
|
||||
#
|
||||
|
||||
#
|
||||
# Lwext4 filesystem
|
||||
#
|
||||
|
||||
#
|
||||
# APP Framework
|
||||
#
|
||||
|
||||
#
|
||||
# Perception
|
||||
#
|
||||
# CONFIG_PERCEPTION_SENSORDEVICE is not set
|
||||
|
||||
#
|
||||
# connection
|
||||
#
|
||||
# CONFIG_CONNECTION_AT is not set
|
||||
# CONFIG_CONNECTION_MQTT is not set
|
||||
|
||||
#
|
||||
# medium communication
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# Intelligence
|
||||
#
|
||||
|
||||
#
|
||||
# Control
|
||||
#
|
||||
|
||||
#
|
||||
# Lib
|
||||
#
|
||||
CONFIG_LIB=y
|
||||
CONFIG_LIB_POSIX=y
|
||||
CONFIG_LIB_NEWLIB=y
|
||||
|
||||
# CONFIG_LITTLEVGL2RTT_USING_DEMO=y
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
mainmenu "XiUOS Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config KERNEL_DIR
|
||||
string
|
||||
option env="KERNEL_ROOT"
|
||||
default "../.."
|
||||
|
||||
config BOARD_CORTEX_M3_EVB
|
||||
bool
|
||||
select ARCH_ARM
|
||||
default y
|
||||
|
||||
config KERNEL_CONSOLE_DEVICE_NAME
|
||||
string
|
||||
default "uart0"
|
||||
|
||||
|
||||
source "$KERNEL_DIR/arch/Kconfig"
|
||||
|
||||
menu "cortex-m3 emulator feature"
|
||||
source "$BSP_DIR/third_party_driver/Kconfig"
|
||||
|
||||
menu "config default board resources"
|
||||
menu "config board app name"
|
||||
config BOARD_APP_NAME
|
||||
string "config board app name"
|
||||
default "/XiUOS_cortex-m3-emulator_app.bin"
|
||||
endmenu
|
||||
|
||||
menu "config board service table"
|
||||
config SERVICE_TABLE_ADDRESS
|
||||
hex "board service table address"
|
||||
default 0x2007F0000
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
config __STACKSIZE__
|
||||
int "stack size for interrupt"
|
||||
default 4096
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
menu "Hardware feature"
|
||||
source "$KERNEL_DIR/resources/Kconfig"
|
||||
endmenu
|
||||
|
||||
source "$KERNEL_DIR/Kconfig"
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
SRC_DIR := third_party_driver
|
||||
|
||||
SRC_FILES := board.c connect_uart.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,187 @@
|
|||
# 从零开始构建矽璓工业物联操作系统：使用ARM架构的cortex-m3 emulator
|
||||
|
||||
# cortex-m3 emulator
|
||||
|
||||
[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。
|
||||
|
||||
## 1. 简介
|
||||
|
||||
QEMU 是一个通用的开源模拟器和虚拟化工具。目前QEMU已经可以较完整的支持ARM cortex-m3架构。XiUOS同样支持运行在QEMU上
|
||||
|
||||
| 硬件 | 描述 |
|
||||
| -- | -- |
|
||||
|芯片型号| lm3s6965evb |
|
||||
|架构| cortex-m3 |
|
||||
|主频| 50MHz |
|
||||
|片内SRAM| 64KB |
|
||||
| 外设支持 | UART |
|
||||
|
||||
XiUOS板级当前支持使用UART。
|
||||
|
||||
## 2. 开发环境搭建
|
||||
|
||||
### 推荐使用：
|
||||
|
||||
**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop)
|
||||
|
||||
更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改）
|
||||
|
||||
第一步:打开sources.list文件
|
||||
|
||||
```c
|
||||
sudo vim /etc/apt/sources.list
|
||||
```
|
||||
|
||||
第二步:将以下内容复制到sources.list文件
|
||||
|
||||
```c
|
||||
deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
|
||||
deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
|
||||
deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
|
||||
deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
|
||||
deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
|
||||
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
|
||||
```
|
||||
|
||||
第三步:更新源和系统软件
|
||||
|
||||
```c
|
||||
sudo apt-get update
|
||||
sudo apt-get upgrade
|
||||
```
|
||||
|
||||
**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb)
|
||||
|
||||
### 依赖包安装：
|
||||
|
||||
```
|
||||
$ sudo apt install build-essential pkg-config git
|
||||
$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
|
||||
```
|
||||
|
||||
**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
|
||||
|
||||
新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：
|
||||
|
||||
```c
|
||||
mkdir test && cd test
|
||||
git clone https://git.trustie.net/xuos/xiuos.git
|
||||
```
|
||||
|
||||
打开源码文件包可以看到以下目录：
|
||||
| 名称 | 说明 |
|
||||
| -- | -- |
|
||||
| application | 应用代码 |
|
||||
| board | 板级支持包 |
|
||||
| framework | 应用框架 |
|
||||
| fs | 文件系统 |
|
||||
| kernel | 内核源码 |
|
||||
| resources | 驱动文件 |
|
||||
| tool | 系统工具 |
|
||||
|
||||
使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示：
|
||||
|
||||
<div align= "center">
|
||||
<img src = img/vscode.jpg width =1000>
|
||||
</div>
|
||||
|
||||
### 裁减配置工具的下载
|
||||
|
||||
裁减配置工具：
|
||||
|
||||
**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下：
|
||||
|
||||
```c
|
||||
mkdir kfrontends && cd kfrontends
|
||||
git clone https://git.trustie.net/xuos/kconfig-frontends.git
|
||||
```
|
||||
|
||||
下载源码后按以下步骤执行软件安装：
|
||||
|
||||
```c
|
||||
cd kconfig-frontends
|
||||
./xs_build.sh
|
||||
```
|
||||
|
||||
### 编译工具链：
|
||||
|
||||
ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。
|
||||
|
||||
```shell
|
||||
$ sudo apt install gcc-arm-none-eabi
|
||||
```
|
||||
|
||||
## 编译说明
|
||||
|
||||
### 编辑环境：`Ubuntu18.04`
|
||||
|
||||
### 编译工具链：`arm-none-eabi-gcc`
|
||||
使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目
|
||||
|
||||
|
||||
编译步骤：
|
||||
|
||||
1.在VScode命令终端中执行以下命令，生成配置文件
|
||||
|
||||
```c
|
||||
make BOARD=cortex-m3-emulator menuconfig
|
||||
```
|
||||
|
||||
2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
|
||||
|
||||
|
||||
|
||||
退出时选择`yes`保存上面所配置的内容，如下图所示：
|
||||
|
||||
|
||||
|
||||
3.继续执行以下命令，进行编译
|
||||
|
||||
```
|
||||
make BOARD=cortex-m3-emulator
|
||||
```
|
||||
|
||||
4.如果编译正确无误，会产生XiUOS_cortex-m3-emulator.elf、XiUOS_cortex-m3-emulator.bin文件。
|
||||
|
||||
## 3. 运行
|
||||
|
||||
### 3.1 安装QEMU
|
||||
|
||||
```
|
||||
sudo apt install qemu-system-arm
|
||||
```
|
||||
|
||||
### 3.2 运行结果
|
||||
|
||||
通过以下命令启动QEMU并加载XiUOS ELF文件
|
||||
|
||||
```
|
||||
qemu-system-arm -machine lm3s6965evb -nographic -kernel build/XiUOS_cortex-m3-emulator.elf
|
||||
```
|
||||
|
||||
QEMU运行起来后将会在终端上看到信息打印输出
|
||||
|
||||
|
||||
|
||||
### 3.3 调试
|
||||
|
||||
通过QEMU可以方便的对XiUOS进行调试，首先安装gdb调试工具
|
||||
```
|
||||
sudo apt install gdb-multiarch
|
||||
```
|
||||
|
||||
并通过以下命令启动QEMU
|
||||
|
||||
```
|
||||
qemu-system-arm -machine lm3s6965evb -nographic -kernel build/XiUOS_cortex-m3-emulator.elf -s -S
|
||||
```
|
||||
|
||||
然后要重新开启另一个linux系统终端一个终端，执行`riscv-none-embed-gdb`命令
|
||||
|
||||
```
|
||||
gdb-multiarch build/XiUOS_cortex-m3-emulator.elf -ex "target remote localhost:1234"
|
||||
```
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.c
|
||||
* @brief support cortex-m3-emulator init configure and start-up
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-13
|
||||
*/
|
||||
|
||||
|
||||
#include <board.h>
|
||||
#include <xiuos.h>
|
||||
#include <device.h>
|
||||
#include <arch_interrupt.h>
|
||||
|
||||
void SysTick_Handler(int irqn, void *arg)
|
||||
{
|
||||
TickAndTaskTimesliceUpdate();
|
||||
}
|
||||
DECLARE_HW_IRQ(SYSTICK_IRQN, SysTick_Handler, NONE);
|
||||
|
||||
void InitBoardHardware()
|
||||
{
|
||||
extern int InitHwUart(void);
|
||||
InitHwUart();
|
||||
InstallConsole(SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1, SERIAL_DEVICE_NAME_1);
|
||||
InitBoardMemory((void*)LM3S_SRAM_START, (void*)LM3S_SRAM_END);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.h
|
||||
* @brief define cortex-m3-emulator init configure and start-up function
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-13
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
|
||||
extern void *__bss_end;
|
||||
extern void *_heap_end;
|
||||
#define MEM_OFFSET 0x20002000
|
||||
#define LM3S_SRAM_START ( ( ((unsigned long)(&__bss_end)) > MEM_OFFSET)? (unsigned long)(&__bss_end):(MEM_OFFSET) )
|
||||
#define LM3S_SRAM_END ( &_heap_end )
|
||||
|
||||
#define BSP_USING_UART1
|
||||
#define SERIAL_BUS_NAME_1 "uart0"
|
||||
#define SERIAL_DRV_NAME_1 "uart0_drv"
|
||||
#define SERIAL_DEVICE_NAME_1 "uart0_dev0"
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
|
||||
|
||||
export CFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb
|
||||
export AFLAGS := -c -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
|
||||
export LFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_cortex-m3-emulator.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
|
||||
export CXXFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g
|
||||
|
||||
export APPLFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
|
||||
|
||||
|
||||
export DEFINES := -DHAVE_CCONFIG_H
|
||||
|
||||
export ARCH = arm
|
||||
export MCU = cortex-m3
|
||||
|
|
@ -0,0 +1,351 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_uart.c
|
||||
* @brief support cortex_m3_emulator board uart function and register to bus framework
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-10
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <xiuos.h>
|
||||
#include <device.h>
|
||||
#include <inc/hw_types.h>
|
||||
#include <driverlib/gpio.h>
|
||||
#include <driverlib/interrupt.h>
|
||||
#include <driverlib/sysctl.h>
|
||||
#include <driverlib/uart.h>
|
||||
#include <inc/hw_ints.h>
|
||||
#include <inc/hw_memmap.h>
|
||||
#include <inc/hw_uart.h>
|
||||
|
||||
#ifdef BSP_USING_UART1
|
||||
static struct SerialBus serial_bus_1;
|
||||
static struct SerialDriver serial_driver_1;
|
||||
static struct SerialHardwareDevice serial_device_1;
|
||||
#endif
|
||||
#ifdef BSP_USING_UART2
|
||||
static struct SerialBus serial_bus_2;
|
||||
static struct SerialDriver serial_driver_2;
|
||||
static struct SerialHardwareDevice serial_device_2;
|
||||
#endif
|
||||
|
||||
static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
|
||||
{
|
||||
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
|
||||
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
|
||||
|
||||
if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
|
||||
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
|
||||
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
|
||||
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
|
||||
data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
|
||||
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
|
||||
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
|
||||
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
|
||||
}
|
||||
}
|
||||
|
||||
static void UartHandler(struct SerialBus *serial_bus, struct SerialDriver *serial_drv)
|
||||
{
|
||||
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_bus->bus.owner_haldev;
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
|
||||
uint32 status;
|
||||
|
||||
status = UARTIntStatus(serial_cfg->hw_cfg.serial_register_base, RET_TRUE);
|
||||
|
||||
/* clear interrupt status */
|
||||
UARTIntClear(serial_cfg->hw_cfg.serial_register_base, status);
|
||||
|
||||
while (UARTCharsAvail(serial_cfg->hw_cfg.serial_register_base)) {
|
||||
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef BSP_USING_UART1
|
||||
void UartIsr1(int vector, void *param)
|
||||
{
|
||||
/* get serial bus 1 */
|
||||
UartHandler(&serial_bus_1, &serial_driver_1);
|
||||
}
|
||||
DECLARE_HW_IRQ(UART1_IRQn, UartIsr1, NONE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART2
|
||||
void UartIsr2(int irqno)
|
||||
{
|
||||
/* get serial bus 2 */
|
||||
UartHandler(&serial_bus_2, &serial_driver_2);
|
||||
}
|
||||
#endif
|
||||
|
||||
static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
NULL_PARAM_CHECK(serial_drv);
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
|
||||
{
|
||||
NULL_PARAM_CHECK(serial_drv);
|
||||
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
struct HardwareDev *dev = serial_drv->driver.owner_bus->owner_haldev;
|
||||
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev;
|
||||
struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
|
||||
|
||||
if (OPER_CLR_INT == serial_operation_cmd) {
|
||||
if (SIGN_OPER_INT_RX & serial_dev_param->serial_work_mode) {
|
||||
/* disable UART rx interrupt */
|
||||
UARTIntDisable(serial_cfg->hw_cfg.serial_register_base, UART_INT_RX | UART_INT_RT);
|
||||
}
|
||||
} else if (OPER_SET_INT == serial_operation_cmd) {
|
||||
/* enable interrupt */
|
||||
if (UART0_BASE == serial_cfg->hw_cfg.serial_register_base)
|
||||
IntEnable(INT_UART0);
|
||||
else if (UART1_BASE == serial_cfg->hw_cfg.serial_register_base)
|
||||
IntEnable(INT_UART1);
|
||||
|
||||
UARTIntEnable(serial_cfg->hw_cfg.serial_register_base, UART_INT_RX | UART_INT_RT);
|
||||
}
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
NULL_PARAM_CHECK(drv);
|
||||
NULL_PARAM_CHECK(configure_info);
|
||||
|
||||
x_err_t ret = EOK;
|
||||
int serial_operation_cmd;
|
||||
struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
|
||||
|
||||
switch (configure_info->configure_cmd)
|
||||
{
|
||||
case OPE_INT:
|
||||
ret = SerialInit(serial_drv, configure_info);
|
||||
break;
|
||||
case OPE_CFG:
|
||||
serial_operation_cmd = *(int *)configure_info->private_data;
|
||||
ret = SerialConfigure(serial_drv, serial_operation_cmd);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c)
|
||||
{
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
while (UARTCharPutNonBlocking(serial_cfg->hw_cfg.serial_register_base, c) == RET_FALSE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int SerialGetChar(struct SerialHardwareDevice *serial_dev)
|
||||
{
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
long val = UARTCharGetNonBlocking(serial_cfg->hw_cfg.serial_register_base);
|
||||
if (val > 0)
|
||||
return (int)val;
|
||||
else
|
||||
return -1;
|
||||
}
|
||||
|
||||
static const struct SerialDataCfg data_cfg_init =
|
||||
{
|
||||
.serial_baud_rate = BAUD_RATE_115200,
|
||||
.serial_data_bits = DATA_BITS_8,
|
||||
.serial_stop_bits = STOP_BITS_1,
|
||||
.serial_parity_mode = PARITY_NONE,
|
||||
.serial_bit_order = BIT_ORDER_LSB,
|
||||
.serial_invert_mode = NRZ_NORMAL,
|
||||
.serial_buffer_size = SERIAL_RB_BUFSZ,
|
||||
};
|
||||
|
||||
/*manage the serial device operations*/
|
||||
static const struct SerialDrvDone drv_done =
|
||||
{
|
||||
.init = SerialInit,
|
||||
.configure = SerialConfigure,
|
||||
};
|
||||
|
||||
/*manage the serial device hal operations*/
|
||||
static struct SerialHwDevDone hwdev_done =
|
||||
{
|
||||
.put_char = SerialPutChar,
|
||||
.get_char = SerialGetChar,
|
||||
};
|
||||
|
||||
static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
/*Init the serial bus */
|
||||
ret = SerialBusInit(serial_bus, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart SerialBusInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Init the serial driver*/
|
||||
ret = SerialDriverInit(serial_driver, drv_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart SerialDriverInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Attach the serial driver to the serial bus*/
|
||||
ret = SerialDriverAttachToBus(drv_name, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart SerialDriverAttachToBus error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*Attach the serial device to the serial bus*/
|
||||
static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart SerialDeviceInit device %s error %d\n", dev_name, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = SerialDeviceAttachToBus(dev_name, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int InitHwUart(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
#ifdef BSP_USING_UART1
|
||||
memset(&serial_bus_1, 0, sizeof(struct SerialBus));
|
||||
memset(&serial_driver_1, 0, sizeof(struct SerialDriver));
|
||||
memset(&serial_device_1, 0, sizeof(struct SerialHardwareDevice));
|
||||
|
||||
static struct SerialCfgParam serial_cfg_1;
|
||||
memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_1;
|
||||
memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_driver_1.drv_done = &drv_done;
|
||||
serial_driver_1.configure = &SerialDrvConfigure;
|
||||
serial_device_1.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_1.data_cfg = data_cfg_init;
|
||||
|
||||
serial_cfg_1.hw_cfg.serial_register_base = UART0_BASE;
|
||||
serial_driver_1.private_data = (void *)&serial_cfg_1;
|
||||
|
||||
serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
|
||||
|
||||
/* enable UART0 clock */
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
|
||||
|
||||
/* set UART0 pinmux */
|
||||
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
|
||||
|
||||
/* Configure the UART for 115,200, 8-N-1 operation. */
|
||||
UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial_cfg_1.data_cfg.serial_baud_rate,
|
||||
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
|
||||
UART_CONFIG_PAR_NONE));
|
||||
|
||||
ret = BoardSerialBusInit(&serial_bus_1, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart uarths error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_DEVICE_NAME_1);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart uarths error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART2
|
||||
memset(&serial_bus_2, 0, sizeof(struct SerialBus));
|
||||
memset(&serial_driver_2, 0, sizeof(struct SerialDriver));
|
||||
memset(&serial_device_2, 0, sizeof(struct SerialHardwareDevice));
|
||||
|
||||
static struct SerialCfgParam serial_cfg_2;
|
||||
memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_2;
|
||||
memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_driver_2.drv_done = &drv_done;
|
||||
serial_driver_2.configure = &SerialDrvConfigure;
|
||||
serial_device_2.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_2.data_cfg = data_cfg_init;
|
||||
|
||||
serial_cfg_2.hw_cfg.serial_register_base = UART1_BASE;
|
||||
serial_driver_2.private_data = (void *)&serial_cfg_2;
|
||||
|
||||
serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
|
||||
|
||||
ret = BoardSerialBusInit(&serial_bus_2, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart uarths error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_DEVICE_NAME_2);
|
||||
if (EOK != ret) {
|
||||
KPrintf("InitHwUart uarths error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
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|
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|
After Width: | Height: | Size: 21 KiB |
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|
After Width: | Height: | Size: 451 KiB |
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|
After Width: | Height: | Size: 56 KiB |
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rx) : ORIGIN = 0x00000000, LENGTH = 256K
|
||||
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
}
|
||||
OUTPUT_ARCH(arm)
|
||||
|
||||
__SYSTEM_STACKSIZE__ = 0x1000;
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
*(.text .text.*)
|
||||
*(.rodata .rodata*) /* read-only data (constants) */
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
|
||||
/* section information for shell */
|
||||
. = ALIGN(4);
|
||||
_shell_command_start = .;
|
||||
KEEP (*(shellCommand))
|
||||
_shell_command_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
__isrtbl_idx_start = .;
|
||||
KEEP(*(.isrtbl.idx))
|
||||
__isrtbl_start = .;
|
||||
KEEP(*(.isrtbl))
|
||||
__isrtbl_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE(g_service_table_start = ABSOLUTE(.));
|
||||
KEEP(*(.g_service_table))
|
||||
PROVIDE(g_service_table_end = ABSOLUTE(.));
|
||||
|
||||
PROVIDE(_etext = ABSOLUTE(.));
|
||||
|
||||
_etext = .;
|
||||
} > flash = 0
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
_sidata = .;
|
||||
} > flash
|
||||
__exidx_end = .;
|
||||
|
||||
.data : AT (_sidata)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = . ;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
. = ALIGN(4);
|
||||
_edata = . ;
|
||||
} >sram
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = .;
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
} > sram
|
||||
__bss_end = .;
|
||||
_end = .;
|
||||
|
||||
.stack ORIGIN(sram) + LENGTH(sram) - __SYSTEM_STACKSIZE__ :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = __SYSTEM_STACKSIZE__;
|
||||
PROVIDE( _sp = . );
|
||||
} >sram
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_DIR := driverlib
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := gpio.c interrupt.c sysctl.c uart.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// cpu.h - Prototypes for the CPU instruction wrapper functions.
|
||||
//
|
||||
// Copyright (c) 2006-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __CPU_H__
|
||||
#define __CPU_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern unsigned long CPUcpsid(void);
|
||||
extern unsigned long CPUcpsie(void);
|
||||
extern unsigned long CPUprimask(void);
|
||||
extern void CPUwfi(void);
|
||||
extern unsigned long CPUbasepriGet(void);
|
||||
extern void CPUbasepriSet(unsigned long ulNewBasepri);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __CPU_H__
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// debug.h - Macros for assisting debug of the driver library.
|
||||
//
|
||||
// Copyright (c) 2006-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DEBUG_H__
|
||||
#define __DEBUG_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototype for the function that is called when an invalid argument is passed
|
||||
// to an API. This is only used when doing a DEBUG build.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void __error__(char *pcFilename, unsigned long ulLine);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The ASSERT macro, which does the actual assertion checking. Typically, this
|
||||
// will be for procedure arguments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef DEBUG
|
||||
#define ASSERT(expr) { \
|
||||
if(!(expr)) \
|
||||
{ \
|
||||
__error__(__FILE__, __LINE__); \
|
||||
} \
|
||||
}
|
||||
#else
|
||||
#define ASSERT(expr)
|
||||
#endif
|
||||
|
||||
#endif // __DEBUG_H__
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,197 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// gpio.h - Defines and Macros for GPIO API.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __GPIO_H__
|
||||
#define __GPIO_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following values define the bit field for the ucPins argument to several
|
||||
// of the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
|
||||
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
|
||||
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
|
||||
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
|
||||
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
|
||||
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
|
||||
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
|
||||
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
|
||||
// returned from GPIODirModeGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
|
||||
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
|
||||
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
|
||||
// returned from GPIOIntTypeGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
|
||||
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
|
||||
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
|
||||
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
|
||||
#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level
|
||||
#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
|
||||
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
|
||||
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
|
||||
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
|
||||
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
|
||||
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
|
||||
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
|
||||
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
|
||||
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
|
||||
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned long ulPinIO);
|
||||
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
|
||||
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned long ulIntType);
|
||||
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
|
||||
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned long ulStrength,
|
||||
unsigned long ulPadType);
|
||||
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
|
||||
unsigned long *pulStrength,
|
||||
unsigned long *pulPadType);
|
||||
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
|
||||
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPortIntRegister(unsigned long ulPort,
|
||||
void (*pfnIntHandler)(void));
|
||||
extern void GPIOPortIntUnregister(unsigned long ulPort);
|
||||
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned char ucVal);
|
||||
extern void GPIOPinConfigure(unsigned long ulPinConfig);
|
||||
extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
|
||||
unsigned char ucPins);
|
||||
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOADCTriggerDisable(unsigned long ulPort, unsigned char ucPins);
|
||||
|
||||
//****************************************************************************
|
||||
//
|
||||
// The definitions for GPIOPinConfigure previously resided in this file but
|
||||
// have been moved to pin_map.h and made part-specific (in other words, only
|
||||
// those definitions that are valid based on the selected part, as defined by
|
||||
// PART_<partnum>, will be made available). For backwards compatibility,
|
||||
// pin_map.h is included here so that the expected definitions will still be
|
||||
// available (though part-specific now, so some that were previously available
|
||||
// but inappropriate for the given part will not be available).
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#include "pin_map.h"
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __GPIO_H__
|
||||
|
|
@ -0,0 +1,837 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// interrupt.c - Driver for the NVIC Interrupt Controller.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \addtogroup interrupt_api
|
||||
//! @{
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#include "inc/hw_ints.h"
|
||||
#include "inc/hw_nvic.h"
|
||||
#include "inc/hw_types.h"
|
||||
#include "driverlib/cpu.h"
|
||||
#include "driverlib/debug.h"
|
||||
#include "driverlib/interrupt.h"
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is a mapping between priority grouping encodings and the number of
|
||||
// preemption priority bits.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const unsigned long g_pulPriority[] =
|
||||
{
|
||||
NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
|
||||
NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
|
||||
NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is a mapping between interrupt number and the register that contains
|
||||
// the priority encoding for that interrupt.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const unsigned long g_pulRegs[] =
|
||||
{
|
||||
0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
|
||||
NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
|
||||
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13,
|
||||
NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19,
|
||||
NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25,
|
||||
NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31,
|
||||
NVIC_PRI32, NVIC_PRI33, NVIC_PRI34
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is a mapping between interrupt number (for the peripheral interrupts
|
||||
// only) and the register that contains the interrupt enable for that
|
||||
// interrupt.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const unsigned long g_pulEnRegs[] =
|
||||
{
|
||||
NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is a mapping between interrupt number (for the peripheral interrupts
|
||||
// only) and the register that contains the interrupt disable for that
|
||||
// interrupt.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const unsigned long g_pulDisRegs[] =
|
||||
{
|
||||
NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is a mapping between interrupt number (for the peripheral interrupts
|
||||
// only) and the register that contains the interrupt pend for that interrupt.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const unsigned long g_pulPendRegs[] =
|
||||
{
|
||||
NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// This is a mapping between interrupt number (for the peripheral interrupts
|
||||
// only) and the register that contains the interrupt unpend for that
|
||||
// interrupt.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static const unsigned long g_pulUnpendRegs[] =
|
||||
{
|
||||
NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4
|
||||
};
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! \internal
|
||||
//! The default interrupt handler.
|
||||
//!
|
||||
//! This is the default interrupt handler for all interrupts. It simply loops
|
||||
//! forever so that the system state is preserved for observation by a
|
||||
//! debugger. Since interrupts should be disabled before unregistering the
|
||||
//! corresponding handler, this should never be called.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
static void
|
||||
IntDefaultHandler(void)
|
||||
{
|
||||
//
|
||||
// Go into an infinite loop.
|
||||
//
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The processor vector table.
|
||||
//
|
||||
// This contains a list of the handlers for the various interrupt sources in
|
||||
// the system. The layout of this list is defined by the hardware; assertion
|
||||
// of an interrupt causes the processor to start executing directly at the
|
||||
// address given in the corresponding location in this list.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined(ewarm)
|
||||
#pragma data_alignment=1024
|
||||
static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
|
||||
#elif defined(sourcerygxx)
|
||||
static __attribute__((section(".cs3.region-head.ram")))
|
||||
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
|
||||
#elif defined(ccs) || defined(DOXYGEN)
|
||||
#pragma DATA_ALIGN(g_pfnRAMVectors, 1024)
|
||||
#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
|
||||
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
|
||||
#else
|
||||
static __attribute__((section("vtable")))
|
||||
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables the processor interrupt.
|
||||
//!
|
||||
//! This function allows the processor to respond to interrupts. This function
|
||||
//! does not affect the set of interrupts enabled in the interrupt controller;
|
||||
//! it just gates the single interrupt from the controller to the processor.
|
||||
//!
|
||||
//! \note Previously, this function had no return value. As such, it was
|
||||
//! possible to include <tt>interrupt.h</tt> and call this function without
|
||||
//! having included <tt>hw_types.h</tt>. Now that the return is a
|
||||
//! <tt>tBoolean</tt>, a compiler error occurs in this case. The solution
|
||||
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
|
||||
//!
|
||||
//! \return Returns \b true if interrupts were disabled when the function was
|
||||
//! called or \b false if they were initially enabled.
|
||||
//
|
||||
//*****************************************************************************
|
||||
tBoolean
|
||||
IntMasterEnable(void)
|
||||
{
|
||||
//
|
||||
// Enable processor interrupts.
|
||||
//
|
||||
return(CPUcpsie());
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables the processor interrupt.
|
||||
//!
|
||||
//! This function prevents the processor from receiving interrupts. This
|
||||
//! function does not affect the set of interrupts enabled in the interrupt
|
||||
//! controller; it just gates the single interrupt from the controller to the
|
||||
//! processor.
|
||||
//!
|
||||
//! \note Previously, this function had no return value. As such, it was
|
||||
//! possible to include <tt>interrupt.h</tt> and call this function without
|
||||
//! having included <tt>hw_types.h</tt>. Now that the return is a
|
||||
//! <tt>tBoolean</tt>, a compiler error occurs in this case. The solution
|
||||
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
|
||||
//!
|
||||
//! \return Returns \b true if interrupts were already disabled when the
|
||||
//! function was called or \b false if they were initially enabled.
|
||||
//
|
||||
//*****************************************************************************
|
||||
tBoolean
|
||||
IntMasterDisable(void)
|
||||
{
|
||||
//
|
||||
// Disable processor interrupts.
|
||||
//
|
||||
return(CPUcpsid());
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Registers a function to be called when an interrupt occurs.
|
||||
//!
|
||||
//! \param ulInterrupt specifies the interrupt in question.
|
||||
//! \param pfnHandler is a pointer to the function to be called.
|
||||
//!
|
||||
//! This function is used to specify the handler function to be called when the
|
||||
//! given interrupt is asserted to the processor. When the interrupt occurs,
|
||||
//! if it is enabled (via IntEnable()), the handler function is called in
|
||||
//! interrupt context. Because the handler function can preempt other code,
|
||||
//! care must be taken to protect memory or peripherals that are accessed by
|
||||
//! the handler and other non-handler code.
|
||||
//!
|
||||
//! \note The use of this function (directly or indirectly via a peripheral
|
||||
//! driver interrupt register function) moves the interrupt vector table from
|
||||
//! flash to SRAM. Therefore, care must be taken when linking the application
|
||||
//! to ensure that the SRAM vector table is located at the beginning of SRAM;
|
||||
//! otherwise the NVIC does not look in the correct portion of memory for the
|
||||
//! vector table (it requires the vector table be on a 1 kB memory alignment).
|
||||
//! Normally, the SRAM vector table is so placed via the use of linker scripts.
|
||||
//! See the discussion of compile-time versus run-time interrupt handler
|
||||
//! registration in the introduction to this chapter.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
|
||||
{
|
||||
unsigned long ulIdx, ulValue;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ulInterrupt < NUM_INTERRUPTS);
|
||||
|
||||
//
|
||||
// Make sure that the RAM vector table is correctly aligned.
|
||||
//
|
||||
ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0);
|
||||
|
||||
//
|
||||
// See if the RAM vector table has been initialized.
|
||||
//
|
||||
if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors)
|
||||
{
|
||||
//
|
||||
// Copy the vector table from the beginning of FLASH to the RAM vector
|
||||
// table.
|
||||
//
|
||||
ulValue = HWREG(NVIC_VTABLE);
|
||||
for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++)
|
||||
{
|
||||
g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG((ulIdx * 4) +
|
||||
ulValue);
|
||||
}
|
||||
|
||||
//
|
||||
// Point the NVIC at the RAM vector table.
|
||||
//
|
||||
HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors;
|
||||
}
|
||||
|
||||
//
|
||||
// Save the interrupt handler.
|
||||
//
|
||||
g_pfnRAMVectors[ulInterrupt] = pfnHandler;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Unregisters the function to be called when an interrupt occurs.
|
||||
//!
|
||||
//! \param ulInterrupt specifies the interrupt in question.
|
||||
//!
|
||||
//! This function is used to indicate that no handler should be called when the
|
||||
//! given interrupt is asserted to the processor. The interrupt source is
|
||||
//! automatically disabled (via IntDisable()) if necessary.
|
||||
//!
|
||||
//! \sa IntRegister() for important information about registering interrupt
|
||||
//! handlers.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntUnregister(unsigned long ulInterrupt)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ulInterrupt < NUM_INTERRUPTS);
|
||||
|
||||
//
|
||||
// Reset the interrupt handler.
|
||||
//
|
||||
g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the priority grouping of the interrupt controller.
|
||||
//!
|
||||
//! \param ulBits specifies the number of bits of preemptable priority.
|
||||
//!
|
||||
//! This function specifies the split between preemptable priority levels and
|
||||
//! sub-priority levels in the interrupt priority specification. The range of
|
||||
//! the grouping values are dependent upon the hardware implementation; on
|
||||
//! the Stellaris family, three bits are available for hardware interrupt
|
||||
//! prioritization and therefore priority grouping values of three through
|
||||
//! seven have the same effect.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntPriorityGroupingSet(unsigned long ulBits)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ulBits < NUM_PRIORITY);
|
||||
|
||||
//
|
||||
// Set the priority grouping.
|
||||
//
|
||||
HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the priority grouping of the interrupt controller.
|
||||
//!
|
||||
//! This function returns the split between preemptable priority levels and
|
||||
//! sub-priority levels in the interrupt priority specification.
|
||||
//!
|
||||
//! \return The number of bits of preemptable priority.
|
||||
//
|
||||
//*****************************************************************************
|
||||
unsigned long
|
||||
IntPriorityGroupingGet(void)
|
||||
{
|
||||
unsigned long ulLoop, ulValue;
|
||||
|
||||
//
|
||||
// Read the priority grouping.
|
||||
//
|
||||
ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
|
||||
|
||||
//
|
||||
// Loop through the priority grouping values.
|
||||
//
|
||||
for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
|
||||
{
|
||||
//
|
||||
// Stop looping if this value matches.
|
||||
//
|
||||
if(ulValue == g_pulPriority[ulLoop])
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Return the number of priority bits.
|
||||
//
|
||||
return(ulLoop);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the priority of an interrupt.
|
||||
//!
|
||||
//! \param ulInterrupt specifies the interrupt in question.
|
||||
//! \param ucPriority specifies the priority of the interrupt.
|
||||
//!
|
||||
//! This function is used to set the priority of an interrupt. When multiple
|
||||
//! interrupts are asserted simultaneously, the ones with the highest priority
|
||||
//! are processed before the lower priority interrupts. Smaller numbers
|
||||
//! correspond to higher interrupt priorities; priority 0 is the highest
|
||||
//! interrupt priority.
|
||||
//!
|
||||
//! The hardware priority mechanism only looks at the upper N bits of the
|
||||
//! priority level (where N is 3 for the Stellaris family), so any
|
||||
//! prioritization must be performed in those bits. The remaining bits can be
|
||||
//! used to sub-prioritize the interrupt sources, and may be used by the
|
||||
//! hardware priority mechanism on a future part. This arrangement allows
|
||||
//! priorities to migrate to different NVIC implementations without changing
|
||||
//! the gross prioritization of the interrupts.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
|
||||
{
|
||||
unsigned long ulTemp;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
|
||||
|
||||
//
|
||||
// Set the interrupt priority.
|
||||
//
|
||||
ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);
|
||||
ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));
|
||||
ulTemp |= ucPriority << (8 * (ulInterrupt & 3));
|
||||
HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the priority of an interrupt.
|
||||
//!
|
||||
//! \param ulInterrupt specifies the interrupt in question.
|
||||
//!
|
||||
//! This function gets the priority of an interrupt. See IntPrioritySet() for
|
||||
//! a definition of the priority value.
|
||||
//!
|
||||
//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
|
||||
//! specified.
|
||||
//
|
||||
//*****************************************************************************
|
||||
long
|
||||
IntPriorityGet(unsigned long ulInterrupt)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
|
||||
|
||||
//
|
||||
// Return the interrupt priority.
|
||||
//
|
||||
return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &
|
||||
0xFF);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Enables an interrupt.
|
||||
//!
|
||||
//! \param ulInterrupt specifies the interrupt to be enabled.
|
||||
//!
|
||||
//! The specified interrupt is enabled in the interrupt controller. Other
|
||||
//! enables for the interrupt (such as at the peripheral level) are unaffected
|
||||
//! by this function.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntEnable(unsigned long ulInterrupt)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ulInterrupt < NUM_INTERRUPTS);
|
||||
|
||||
//
|
||||
// Determine the interrupt to enable.
|
||||
//
|
||||
if(ulInterrupt == FAULT_MPU)
|
||||
{
|
||||
//
|
||||
// Enable the MemManage interrupt.
|
||||
//
|
||||
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
|
||||
}
|
||||
else if(ulInterrupt == FAULT_BUS)
|
||||
{
|
||||
//
|
||||
// Enable the bus fault interrupt.
|
||||
//
|
||||
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
|
||||
}
|
||||
else if(ulInterrupt == FAULT_USAGE)
|
||||
{
|
||||
//
|
||||
// Enable the usage fault interrupt.
|
||||
//
|
||||
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
|
||||
}
|
||||
else if(ulInterrupt == FAULT_SYSTICK)
|
||||
{
|
||||
//
|
||||
// Enable the System Tick interrupt.
|
||||
//
|
||||
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
|
||||
}
|
||||
else if(ulInterrupt >= 16)
|
||||
{
|
||||
//
|
||||
// Enable the general interrupt.
|
||||
//
|
||||
HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) =
|
||||
1 << ((ulInterrupt - 16) & 31);
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Disables an interrupt.
|
||||
//!
|
||||
//! \param ulInterrupt specifies the interrupt to be disabled.
|
||||
//!
|
||||
//! The specified interrupt is disabled in the interrupt controller. Other
|
||||
//! enables for the interrupt (such as at the peripheral level) are unaffected
|
||||
//! by this function.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntDisable(unsigned long ulInterrupt)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ulInterrupt < NUM_INTERRUPTS);
|
||||
|
||||
//
|
||||
// Determine the interrupt to disable.
|
||||
//
|
||||
if(ulInterrupt == FAULT_MPU)
|
||||
{
|
||||
//
|
||||
// Disable the MemManage interrupt.
|
||||
//
|
||||
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
|
||||
}
|
||||
else if(ulInterrupt == FAULT_BUS)
|
||||
{
|
||||
//
|
||||
// Disable the bus fault interrupt.
|
||||
//
|
||||
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
|
||||
}
|
||||
else if(ulInterrupt == FAULT_USAGE)
|
||||
{
|
||||
//
|
||||
// Disable the usage fault interrupt.
|
||||
//
|
||||
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
|
||||
}
|
||||
else if(ulInterrupt == FAULT_SYSTICK)
|
||||
{
|
||||
//
|
||||
// Disable the System Tick interrupt.
|
||||
//
|
||||
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
|
||||
}
|
||||
else if(ulInterrupt >= 16)
|
||||
{
|
||||
//
|
||||
// Disable the general interrupt.
|
||||
//
|
||||
HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) =
|
||||
1 << ((ulInterrupt - 16) & 31);
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Returns if a peripheral interrupt is enabled.
|
||||
//!
|
||||
//! \param ulInterrupt specifies the interrupt to check.
|
||||
//!
|
||||
//! This function checks if the specified interrupt is enabled in the interrupt
|
||||
//! controller.
|
||||
//!
|
||||
//! \return A non-zero value if the interrupt is enabled.
|
||||
//
|
||||
//*****************************************************************************
|
||||
unsigned long
|
||||
IntIsEnabled(unsigned long ulInterrupt)
|
||||
{
|
||||
unsigned long ulRet;
|
||||
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ulInterrupt < NUM_INTERRUPTS);
|
||||
|
||||
//
|
||||
// Initialize the return value.
|
||||
//
|
||||
ulRet = 0;
|
||||
|
||||
//
|
||||
// Determine the interrupt to disable.
|
||||
//
|
||||
if(ulInterrupt == FAULT_MPU)
|
||||
{
|
||||
//
|
||||
// Check the MemManage interrupt.
|
||||
//
|
||||
ulRet = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_MEM;
|
||||
}
|
||||
else if(ulInterrupt == FAULT_BUS)
|
||||
{
|
||||
//
|
||||
// Check the bus fault interrupt.
|
||||
//
|
||||
ulRet = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_BUS;
|
||||
}
|
||||
else if(ulInterrupt == FAULT_USAGE)
|
||||
{
|
||||
//
|
||||
// Check the usage fault interrupt.
|
||||
//
|
||||
ulRet = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_USAGE;
|
||||
}
|
||||
else if(ulInterrupt == FAULT_SYSTICK)
|
||||
{
|
||||
//
|
||||
// Check the System Tick interrupt.
|
||||
//
|
||||
ulRet = HWREG(NVIC_ST_CTRL) & NVIC_ST_CTRL_INTEN;
|
||||
}
|
||||
else if(ulInterrupt >= 16)
|
||||
{
|
||||
//
|
||||
// Check the general interrupt.
|
||||
//
|
||||
ulRet = HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) &
|
||||
(1 << ((ulInterrupt - 16) & 31));
|
||||
}
|
||||
return(ulRet);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Pends an interrupt.
|
||||
//!
|
||||
//! \param ulInterrupt specifies the interrupt to be pended.
|
||||
//!
|
||||
//! The specified interrupt is pended in the interrupt controller. Pending an
|
||||
//! interrupt causes the interrupt controller to execute the corresponding
|
||||
//! interrupt handler at the next available time, based on the current
|
||||
//! interrupt state priorities. For example, if called by a higher priority
|
||||
//! interrupt handler, the specified interrupt handler is not called until
|
||||
//! after the current interrupt handler has completed execution. The interrupt
|
||||
//! must have been enabled for it to be called.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntPendSet(unsigned long ulInterrupt)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ulInterrupt < NUM_INTERRUPTS);
|
||||
|
||||
//
|
||||
// Determine the interrupt to pend.
|
||||
//
|
||||
if(ulInterrupt == FAULT_NMI)
|
||||
{
|
||||
//
|
||||
// Pend the NMI interrupt.
|
||||
//
|
||||
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
|
||||
}
|
||||
else if(ulInterrupt == FAULT_PENDSV)
|
||||
{
|
||||
//
|
||||
// Pend the PendSV interrupt.
|
||||
//
|
||||
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
|
||||
}
|
||||
else if(ulInterrupt == FAULT_SYSTICK)
|
||||
{
|
||||
//
|
||||
// Pend the SysTick interrupt.
|
||||
//
|
||||
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
|
||||
}
|
||||
else if(ulInterrupt >= 16)
|
||||
{
|
||||
//
|
||||
// Pend the general interrupt.
|
||||
//
|
||||
HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) =
|
||||
1 << ((ulInterrupt - 16) & 31);
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Un-pends an interrupt.
|
||||
//!
|
||||
//! \param ulInterrupt specifies the interrupt to be un-pended.
|
||||
//!
|
||||
//! The specified interrupt is un-pended in the interrupt controller. This
|
||||
//! will cause any previously generated interrupts that have not been handled
|
||||
//! yet (due to higher priority interrupts or the interrupt no having been
|
||||
//! enabled yet) to be discarded.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntPendClear(unsigned long ulInterrupt)
|
||||
{
|
||||
//
|
||||
// Check the arguments.
|
||||
//
|
||||
ASSERT(ulInterrupt < NUM_INTERRUPTS);
|
||||
|
||||
//
|
||||
// Determine the interrupt to unpend.
|
||||
//
|
||||
if(ulInterrupt == FAULT_PENDSV)
|
||||
{
|
||||
//
|
||||
// Unpend the PendSV interrupt.
|
||||
//
|
||||
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
|
||||
}
|
||||
else if(ulInterrupt == FAULT_SYSTICK)
|
||||
{
|
||||
//
|
||||
// Unpend the SysTick interrupt.
|
||||
//
|
||||
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
|
||||
}
|
||||
else if(ulInterrupt >= 16)
|
||||
{
|
||||
//
|
||||
// Unpend the general interrupt.
|
||||
//
|
||||
HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) =
|
||||
1 << ((ulInterrupt - 16) & 31);
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Sets the priority masking level
|
||||
//!
|
||||
//! \param ulPriorityMask is the priority level that is masked.
|
||||
//!
|
||||
//! This function sets the interrupt priority masking level so that all
|
||||
//! interrupts at the specified or lesser priority level are masked. Masking
|
||||
//! interrupts can be used to globally disable a set of interrupts with
|
||||
//! priority below a predetermined threshold. A value of 0 disables priority
|
||||
//! masking.
|
||||
//!
|
||||
//! Smaller numbers correspond to higher interrupt priorities. So for example
|
||||
//! a priority level mask of 4 allows interrupts of priority level 0-3,
|
||||
//! and interrupts with a numerical priority of 4 and greater are blocked.
|
||||
//!
|
||||
//! The hardware priority mechanism only looks at the upper N bits of the
|
||||
//! priority level (where N is 3 for the Stellaris family), so any
|
||||
//! prioritization must be performed in those bits.
|
||||
//!
|
||||
//! \return None.
|
||||
//
|
||||
//*****************************************************************************
|
||||
void
|
||||
IntPriorityMaskSet(unsigned long ulPriorityMask)
|
||||
{
|
||||
CPUbasepriSet(ulPriorityMask);
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
//! Gets the priority masking level
|
||||
//!
|
||||
//! This function gets the current setting of the interrupt priority masking
|
||||
//! level. The value returned is the priority level such that all interrupts
|
||||
//! of that and lesser priority are masked. A value of 0 means that priority
|
||||
//! masking is disabled.
|
||||
//!
|
||||
//! Smaller numbers correspond to higher interrupt priorities. So for example
|
||||
//! a priority level mask of 4 allows interrupts of priority level 0-3,
|
||||
//! and interrupts with a numerical priority of 4 and greater are blocked.
|
||||
//!
|
||||
//! The hardware priority mechanism only looks at the upper N bits of the
|
||||
//! priority level (where N is 3 for the Stellaris family), so any
|
||||
//! prioritization must be performed in those bits.
|
||||
//!
|
||||
//! \return Returns the value of the interrupt priority level mask.
|
||||
//
|
||||
//*****************************************************************************
|
||||
unsigned long
|
||||
IntPriorityMaskGet(void)
|
||||
{
|
||||
return(CPUbasepriGet());
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Close the Doxygen group.
|
||||
//! @}
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __INTERRUPT_H__
|
||||
#define __INTERRUPT_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macro to generate an interrupt priority mask based on the number of bits
|
||||
// of priority supported by the hardware.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern tBoolean IntMasterEnable(void);
|
||||
extern tBoolean IntMasterDisable(void);
|
||||
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
|
||||
extern void IntUnregister(unsigned long ulInterrupt);
|
||||
extern void IntPriorityGroupingSet(unsigned long ulBits);
|
||||
extern unsigned long IntPriorityGroupingGet(void);
|
||||
extern void IntPrioritySet(unsigned long ulInterrupt,
|
||||
unsigned char ucPriority);
|
||||
extern long IntPriorityGet(unsigned long ulInterrupt);
|
||||
extern void IntEnable(unsigned long ulInterrupt);
|
||||
extern void IntDisable(unsigned long ulInterrupt);
|
||||
extern unsigned long IntIsEnabled(unsigned long ulInterrupt);
|
||||
extern void IntPendSet(unsigned long ulInterrupt);
|
||||
extern void IntPendClear(unsigned long ulInterrupt);
|
||||
extern void IntPriorityMaskSet(unsigned long ulPriorityMask);
|
||||
extern unsigned long IntPriorityMaskGet(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __INTERRUPT_H__
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,642 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// sysctl.h - Prototypes for the system control driver.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __SYSCTL_H__
|
||||
#define __SYSCTL_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the
|
||||
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
|
||||
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
|
||||
// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
|
||||
// is 3) can only be used with the SysCtlPeripheralPresent() API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
|
||||
#endif
|
||||
#define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0
|
||||
#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module
|
||||
#ifndef DEPRECATED
|
||||
#define SYSCTL_PERIPH_ADC 0x00100001 // ADC
|
||||
#endif
|
||||
#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0
|
||||
#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1
|
||||
#ifndef DEPRECATED
|
||||
#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
|
||||
#endif
|
||||
#define SYSCTL_PERIPH_PWM0 0x00100010 // PWM
|
||||
#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
|
||||
#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
|
||||
#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
|
||||
#define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1
|
||||
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
|
||||
#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
|
||||
#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2
|
||||
#ifndef DEPRECATED
|
||||
#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
|
||||
#endif
|
||||
#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0
|
||||
#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1
|
||||
#ifndef DEPRECATED
|
||||
#define SYSCTL_PERIPH_QEI 0x10000100 // QEI
|
||||
#endif
|
||||
#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0
|
||||
#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1
|
||||
#ifndef DEPRECATED
|
||||
#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
|
||||
#endif
|
||||
#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0
|
||||
#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1
|
||||
#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0
|
||||
#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1
|
||||
#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2
|
||||
#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3
|
||||
#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0
|
||||
#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1
|
||||
#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2
|
||||
#define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0
|
||||
#define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0
|
||||
#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
|
||||
#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
|
||||
#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
|
||||
#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
|
||||
#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
|
||||
#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F
|
||||
#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G
|
||||
#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H
|
||||
#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J
|
||||
#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA
|
||||
#define SYSCTL_PERIPH_USB0 0x20100001 // USB0
|
||||
#define SYSCTL_PERIPH_ETH 0x20105000 // Ethernet
|
||||
#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588
|
||||
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
|
||||
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
|
||||
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
|
||||
#define SYSCTL_PERIPH2_ADC0 0xf0003800 // ADC 0
|
||||
#define SYSCTL_PERIPH2_ADC1 0xf0003801 // ADC 1
|
||||
#define SYSCTL_PERIPH2_CAN0 0xf0003400 // CAN 0
|
||||
#define SYSCTL_PERIPH2_CAN1 0xf0003401 // CAN 1
|
||||
#define SYSCTL_PERIPH2_CAN2 0xf0003402 // CAN 2
|
||||
#define SYSCTL_PERIPH2_COMP0 0xf0003c00 // Analog comparator 0
|
||||
#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0
|
||||
#define SYSCTL_PERIPH2_EPI0 0xf0001000 // EPI0
|
||||
#define SYSCTL_PERIPH2_ETH 0xf0002c00 // ETH
|
||||
#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0
|
||||
#define SYSCTL_PERIPH2_GPIOA 0xf0000800 // GPIO A
|
||||
#define SYSCTL_PERIPH2_GPIOB 0xf0000801 // GPIO B
|
||||
#define SYSCTL_PERIPH2_GPIOC 0xf0000802 // GPIO C
|
||||
#define SYSCTL_PERIPH2_GPIOD 0xf0000803 // GPIO D
|
||||
#define SYSCTL_PERIPH2_GPIOE 0xf0000804 // GPIO E
|
||||
#define SYSCTL_PERIPH2_GPIOF 0xf0000805 // GPIO F
|
||||
#define SYSCTL_PERIPH2_GPIOG 0xf0000806 // GPIO G
|
||||
#define SYSCTL_PERIPH2_GPIOH 0xf0000807 // GPIO H
|
||||
#define SYSCTL_PERIPH2_GPIOJ 0xf0000808 // GPIO J
|
||||
#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K
|
||||
#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L
|
||||
#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M
|
||||
#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N
|
||||
#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P
|
||||
#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q
|
||||
#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R
|
||||
#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S
|
||||
#define SYSCTL_PERIPH2_HIB 0xf0001400 // Hibernation module
|
||||
#define SYSCTL_PERIPH2_I2C0 0xf0002000 // I2C 0
|
||||
#define SYSCTL_PERIPH2_I2C1 0xf0002001 // I2C 1
|
||||
#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2
|
||||
#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3
|
||||
#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4
|
||||
#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5
|
||||
#define SYSCTL_PERIPH2_I2S0 0xf0002400 // I2S0
|
||||
#define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0
|
||||
#define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0
|
||||
#define SYSCTL_PERIPH2_PWM0 0xf0004000 // PWM 0
|
||||
#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1
|
||||
#define SYSCTL_PERIPH2_QEI0 0xf0004400 // QEI 0
|
||||
#define SYSCTL_PERIPH2_QEI1 0xf0004401 // QEI 1
|
||||
#define SYSCTL_PERIPH2_SSI0 0xf0001c00 // SSI 0
|
||||
#define SYSCTL_PERIPH2_SSI1 0xf0001c01 // SSI 1
|
||||
#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2
|
||||
#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3
|
||||
#define SYSCTL_PERIPH2_TIMER0 0xf0000400 // Timer 0
|
||||
#define SYSCTL_PERIPH2_TIMER1 0xf0000401 // Timer 1
|
||||
#define SYSCTL_PERIPH2_TIMER2 0xf0000402 // Timer 2
|
||||
#define SYSCTL_PERIPH2_TIMER3 0xf0000403 // Timer 3
|
||||
#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4
|
||||
#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5
|
||||
#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0
|
||||
#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1
|
||||
#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2
|
||||
#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3
|
||||
#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4
|
||||
#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5
|
||||
#define SYSCTL_PERIPH2_UART0 0xf0001800 // UART 0
|
||||
#define SYSCTL_PERIPH2_UART1 0xf0001801 // UART 1
|
||||
#define SYSCTL_PERIPH2_UART2 0xf0001802 // UART 2
|
||||
#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3
|
||||
#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4
|
||||
#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5
|
||||
#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6
|
||||
#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7
|
||||
#define SYSCTL_PERIPH2_UDMA 0xf0000c00 // uDMA
|
||||
#define SYSCTL_PERIPH2_USB0 0xf0002800 // USB 0
|
||||
#define SYSCTL_PERIPH2_WDOG0 0xf0000000 // Watchdog 0
|
||||
#define SYSCTL_PERIPH2_WDOG1 0xf0000001 // Watchdog 1
|
||||
#define SYSCTL_PERIPH2_HIBERNATE \
|
||||
0xf0001400 // Hibernate
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlPinPresent() API
|
||||
// as the ulPin parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
|
||||
#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
|
||||
#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
|
||||
#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
|
||||
#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
|
||||
#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
|
||||
#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin
|
||||
#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin
|
||||
#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
|
||||
#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
|
||||
#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
|
||||
#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
|
||||
#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
|
||||
#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
|
||||
#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
|
||||
#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
|
||||
#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
|
||||
#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin
|
||||
#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
|
||||
#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
|
||||
#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
|
||||
#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
|
||||
#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
|
||||
#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
|
||||
#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
|
||||
#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
|
||||
#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
|
||||
#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
|
||||
#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
|
||||
#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
|
||||
#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
|
||||
#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
|
||||
#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlLDOSet() API as
|
||||
// the ulVoltage value, or returned by the SysCtlLDOGet() API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
|
||||
#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
|
||||
#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
|
||||
#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
|
||||
#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
|
||||
#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
|
||||
#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
|
||||
#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
|
||||
#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
|
||||
#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
|
||||
#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlLDOConfigSet() API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
|
||||
#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlIntEnable(),
|
||||
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
|
||||
// by the SysCtlIntStatus() API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt
|
||||
#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt
|
||||
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
|
||||
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
|
||||
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
|
||||
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
|
||||
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
|
||||
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
|
||||
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlResetCauseClear()
|
||||
// API or returned by the SysCtlResetCauseGet() API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
|
||||
#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset
|
||||
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
|
||||
#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset
|
||||
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
|
||||
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
|
||||
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
|
||||
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
|
||||
// API as the ulConfig parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
|
||||
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlPWMClockSet() API
|
||||
// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
|
||||
// API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
|
||||
#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
|
||||
#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
|
||||
#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
|
||||
#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
|
||||
#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
|
||||
#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlADCSpeedSet() API
|
||||
// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
|
||||
// API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_ADCSPEED_1MSPS 0x00000F00 // 1,000,000 samples per second
|
||||
#define SYSCTL_ADCSPEED_500KSPS 0x00000A00 // 500,000 samples per second
|
||||
#define SYSCTL_ADCSPEED_250KSPS 0x00000500 // 250,000 samples per second
|
||||
#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlClockSet() API as
|
||||
// the ulConfig parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
|
||||
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
|
||||
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
|
||||
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
|
||||
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
|
||||
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
|
||||
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
|
||||
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
|
||||
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
|
||||
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
|
||||
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
|
||||
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
|
||||
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
|
||||
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
|
||||
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
|
||||
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
|
||||
#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
|
||||
#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
|
||||
#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
|
||||
#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
|
||||
#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
|
||||
#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
|
||||
#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
|
||||
#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
|
||||
#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
|
||||
#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
|
||||
#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
|
||||
#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
|
||||
#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
|
||||
#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
|
||||
#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
|
||||
#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
|
||||
#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
|
||||
#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
|
||||
#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
|
||||
#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
|
||||
#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
|
||||
#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
|
||||
#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
|
||||
#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
|
||||
#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
|
||||
#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
|
||||
#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
|
||||
#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
|
||||
#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
|
||||
#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
|
||||
#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
|
||||
#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
|
||||
#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
|
||||
#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
|
||||
#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
|
||||
#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
|
||||
#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
|
||||
#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
|
||||
#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
|
||||
#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
|
||||
#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
|
||||
#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
|
||||
#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
|
||||
#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
|
||||
#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
|
||||
#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
|
||||
#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
|
||||
#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
|
||||
#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5
|
||||
#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5
|
||||
#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5
|
||||
#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5
|
||||
#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5
|
||||
#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5
|
||||
#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5
|
||||
#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5
|
||||
#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5
|
||||
#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5
|
||||
#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5
|
||||
#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5
|
||||
#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5
|
||||
#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5
|
||||
#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5
|
||||
#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5
|
||||
#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5
|
||||
#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5
|
||||
#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5
|
||||
#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5
|
||||
#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5
|
||||
#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5
|
||||
#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5
|
||||
#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5
|
||||
#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5
|
||||
#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5
|
||||
#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5
|
||||
#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5
|
||||
#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5
|
||||
#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5
|
||||
#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5
|
||||
#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5
|
||||
#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5
|
||||
#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5
|
||||
#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5
|
||||
#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5
|
||||
#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5
|
||||
#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5
|
||||
#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5
|
||||
#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5
|
||||
#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5
|
||||
#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5
|
||||
#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5
|
||||
#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5
|
||||
#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5
|
||||
#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5
|
||||
#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5
|
||||
#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5
|
||||
#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5
|
||||
#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5
|
||||
#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5
|
||||
#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5
|
||||
#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5
|
||||
#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5
|
||||
#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5
|
||||
#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5
|
||||
#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5
|
||||
#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5
|
||||
#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5
|
||||
#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5
|
||||
#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5
|
||||
#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5
|
||||
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
|
||||
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
|
||||
#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
|
||||
#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
|
||||
#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
|
||||
#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
|
||||
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
|
||||
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
|
||||
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
|
||||
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
|
||||
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
|
||||
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
|
||||
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
|
||||
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
|
||||
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
|
||||
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
|
||||
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
|
||||
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
|
||||
#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
|
||||
#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
|
||||
#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
|
||||
#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
|
||||
#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
|
||||
#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
|
||||
#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
|
||||
#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz
|
||||
#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz
|
||||
#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz
|
||||
#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz
|
||||
#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
|
||||
#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
|
||||
#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
|
||||
#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
|
||||
#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
|
||||
#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
|
||||
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
|
||||
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are values that can be passed to the SysCtlDeepSleepClockSet()
|
||||
// API as the ulConfig parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1
|
||||
#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2
|
||||
#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3
|
||||
#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4
|
||||
#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5
|
||||
#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6
|
||||
#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7
|
||||
#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8
|
||||
#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9
|
||||
#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10
|
||||
#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11
|
||||
#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12
|
||||
#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13
|
||||
#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14
|
||||
#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15
|
||||
#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16
|
||||
#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17
|
||||
#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18
|
||||
#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19
|
||||
#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20
|
||||
#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21
|
||||
#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22
|
||||
#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23
|
||||
#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24
|
||||
#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25
|
||||
#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26
|
||||
#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27
|
||||
#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28
|
||||
#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29
|
||||
#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30
|
||||
#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31
|
||||
#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32
|
||||
#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33
|
||||
#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34
|
||||
#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35
|
||||
#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36
|
||||
#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37
|
||||
#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38
|
||||
#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39
|
||||
#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40
|
||||
#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41
|
||||
#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42
|
||||
#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43
|
||||
#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44
|
||||
#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45
|
||||
#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46
|
||||
#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47
|
||||
#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48
|
||||
#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49
|
||||
#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50
|
||||
#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51
|
||||
#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52
|
||||
#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53
|
||||
#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54
|
||||
#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55
|
||||
#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56
|
||||
#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57
|
||||
#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58
|
||||
#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59
|
||||
#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60
|
||||
#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61
|
||||
#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62
|
||||
#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63
|
||||
#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64
|
||||
#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc
|
||||
#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc
|
||||
#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
|
||||
#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz
|
||||
#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern unsigned long SysCtlSRAMSizeGet(void);
|
||||
extern unsigned long SysCtlFlashSizeGet(void);
|
||||
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
|
||||
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
|
||||
extern tBoolean SysCtlPeripheralReady(unsigned long ulPeripheral);
|
||||
extern void SysCtlPeripheralPowerOn(unsigned long ulPeripheral);
|
||||
extern void SysCtlPeripheralPowerOff(unsigned long ulPeripheral);
|
||||
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
|
||||
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
|
||||
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
|
||||
extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
|
||||
extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
|
||||
extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
|
||||
extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
|
||||
extern void SysCtlPeripheralClockGating(tBoolean bEnable);
|
||||
extern void SysCtlIntRegister(void (*pfnHandler)(void));
|
||||
extern void SysCtlIntUnregister(void);
|
||||
extern void SysCtlIntEnable(unsigned long ulInts);
|
||||
extern void SysCtlIntDisable(unsigned long ulInts);
|
||||
extern void SysCtlIntClear(unsigned long ulInts);
|
||||
extern unsigned long SysCtlIntStatus(tBoolean bMasked);
|
||||
extern void SysCtlLDOSet(unsigned long ulVoltage);
|
||||
extern unsigned long SysCtlLDOGet(void);
|
||||
extern void SysCtlLDOConfigSet(unsigned long ulConfig);
|
||||
extern void SysCtlReset(void);
|
||||
extern void SysCtlSleep(void);
|
||||
extern void SysCtlDeepSleep(void);
|
||||
extern unsigned long SysCtlResetCauseGet(void);
|
||||
extern void SysCtlResetCauseClear(unsigned long ulCauses);
|
||||
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
|
||||
unsigned long ulDelay);
|
||||
extern void SysCtlDelay(unsigned long ulCount);
|
||||
extern void SysCtlMOSCConfigSet(unsigned long ulConfig);
|
||||
extern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType);
|
||||
extern void SysCtlClockSet(unsigned long ulConfig);
|
||||
extern unsigned long SysCtlClockGet(void);
|
||||
extern void SysCtlDeepSleepClockSet(unsigned long ulConfig);
|
||||
extern void SysCtlPWMClockSet(unsigned long ulConfig);
|
||||
extern unsigned long SysCtlPWMClockGet(void);
|
||||
extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
|
||||
extern unsigned long SysCtlADCSpeedGet(void);
|
||||
extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
|
||||
extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
|
||||
extern void SysCtlPLLVerificationSet(tBoolean bEnable);
|
||||
extern void SysCtlClkVerificationClear(void);
|
||||
extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
|
||||
extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
|
||||
extern void SysCtlUSBPLLEnable(void);
|
||||
extern void SysCtlUSBPLLDisable(void);
|
||||
extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock,
|
||||
unsigned long ulMClk);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __SYSCTL_H__
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,275 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// uart.h - Defines and Macros for the UART.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __UART_H__
|
||||
#define __UART_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
|
||||
// as the ulIntFlags parameter, and returned from UARTIntStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt
|
||||
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
|
||||
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
|
||||
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
|
||||
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
|
||||
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
|
||||
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
|
||||
#define UART_INT_RX 0x010 // Receive Interrupt Mask
|
||||
#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask
|
||||
#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask
|
||||
#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
|
||||
#define UART_INT_RI 0x001 // RI Modem Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
|
||||
// and returned by UARTConfigGetExpClk in the pulConfig parameter.
|
||||
// Additionally, the UART_CONFIG_PAR_* subset can be passed to
|
||||
// UARTParityModeSet as the ulParity parameter, and are returned by
|
||||
// UARTParityModeGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
|
||||
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
|
||||
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
|
||||
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
|
||||
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
|
||||
#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
|
||||
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
|
||||
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
|
||||
#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
|
||||
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
|
||||
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
|
||||
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
|
||||
#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
|
||||
#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
|
||||
// returned by UARTFIFOLevelGet in the pulTxLevel.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
|
||||
#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
|
||||
#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
|
||||
#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
|
||||
#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
|
||||
// returned by UARTFIFOLevelGet in the pulRxLevel.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
|
||||
#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
|
||||
#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
|
||||
#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
|
||||
#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
|
||||
#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
|
||||
#define UART_DMA_RX 0x00000001 // Enable DMA for receive
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values returned from UARTRxErrorGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_RXERROR_OVERRUN 0x00000008
|
||||
#define UART_RXERROR_BREAK 0x00000004
|
||||
#define UART_RXERROR_PARITY 0x00000002
|
||||
#define UART_RXERROR_FRAMING 0x00000001
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTHandshakeOutputsSet() or returned from
|
||||
// UARTHandshakeOutputGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_OUTPUT_RTS 0x00000800
|
||||
#define UART_OUTPUT_DTR 0x00000400
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be returned from UARTHandshakeInputsGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_INPUT_RI 0x00000100
|
||||
#define UART_INPUT_DCD 0x00000004
|
||||
#define UART_INPUT_DSR 0x00000002
|
||||
#define UART_INPUT_CTS 0x00000001
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTFlowControl() or returned from
|
||||
// UARTFlowControlGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FLOWCONTROL_TX 0x00008000
|
||||
#define UART_FLOWCONTROL_RX 0x00004000
|
||||
#define UART_FLOWCONTROL_NONE 0x00000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTTxIntModeSet() or returned from
|
||||
// UARTTxIntModeGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_TXINT_MODE_FIFO 0x00000000
|
||||
#define UART_TXINT_MODE_EOT 0x00000010
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTClockSourceSet() or returned from
|
||||
// UARTClockSourceGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_CLOCK_SYSTEM 0x00000000
|
||||
#define UART_CLOCK_PIOSC 0x00000005
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// API Function prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
|
||||
extern unsigned long UARTParityModeGet(unsigned long ulBase);
|
||||
extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
|
||||
unsigned long ulRxLevel);
|
||||
extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
|
||||
unsigned long *pulRxLevel);
|
||||
extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
|
||||
unsigned long ulBaud, unsigned long ulConfig);
|
||||
extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
|
||||
unsigned long *pulBaud,
|
||||
unsigned long *pulConfig);
|
||||
extern void UARTEnable(unsigned long ulBase);
|
||||
extern void UARTDisable(unsigned long ulBase);
|
||||
extern void UARTFIFOEnable(unsigned long ulBase);
|
||||
extern void UARTFIFODisable(unsigned long ulBase);
|
||||
extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);
|
||||
extern void UARTDisableSIR(unsigned long ulBase);
|
||||
extern tBoolean UARTCharsAvail(unsigned long ulBase);
|
||||
extern tBoolean UARTSpaceAvail(unsigned long ulBase);
|
||||
extern long UARTCharGetNonBlocking(unsigned long ulBase);
|
||||
extern long UARTCharGet(unsigned long ulBase);
|
||||
extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
|
||||
unsigned char ucData);
|
||||
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
|
||||
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
|
||||
extern tBoolean UARTBusy(unsigned long ulBase);
|
||||
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
|
||||
extern void UARTIntUnregister(unsigned long ulBase);
|
||||
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
|
||||
extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
|
||||
extern unsigned long UARTRxErrorGet(unsigned long ulBase);
|
||||
extern void UARTRxErrorClear(unsigned long ulBase);
|
||||
extern void UARTSmartCardEnable(unsigned long ulBase);
|
||||
extern void UARTSmartCardDisable(unsigned long ulBase);
|
||||
extern void UARTModemControlSet(unsigned long ulBase,
|
||||
unsigned long ulControl);
|
||||
extern void UARTModemControlClear(unsigned long ulBase,
|
||||
unsigned long ulControl);
|
||||
extern unsigned long UARTModemControlGet(unsigned long ulBase);
|
||||
extern unsigned long UARTModemStatusGet(unsigned long ulBase);
|
||||
extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
|
||||
extern unsigned long UARTFlowControlGet(unsigned long ulBase);
|
||||
extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
|
||||
extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
|
||||
extern void UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource);
|
||||
extern unsigned long UARTClockSourceGet(unsigned long ulBase);
|
||||
extern void UART9BitEnable(unsigned long ulBase);
|
||||
extern void UART9BitDisable(unsigned long ulBase);
|
||||
extern void UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr,
|
||||
unsigned char ucMask);
|
||||
extern void UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Several UART APIs have been renamed, with the original function name being
|
||||
// deprecated. These defines provide backward compatibility.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#include "driverlib/sysctl.h"
|
||||
#define UARTConfigSet(a, b, c) \
|
||||
UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
|
||||
#define UARTConfigGet(a, b, c) \
|
||||
UARTConfigGetExpClk(a, SysCtlClockGet(), b, c)
|
||||
#define UARTCharNonBlockingGet(a) \
|
||||
UARTCharGetNonBlocking(a)
|
||||
#define UARTCharNonBlockingPut(a, b) \
|
||||
UARTCharPutNonBlocking(a, b)
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __UART_H__
|
||||
|
|
@ -0,0 +1,192 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_gpio.h - Defines and Macros for GPIO hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 10636 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_GPIO_H__
|
||||
#define __HW_GPIO_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the GPIO register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_O_DATA 0x00000000 // GPIO Data
|
||||
#define GPIO_O_DIR 0x00000400 // GPIO Direction
|
||||
#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense
|
||||
#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges
|
||||
#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event
|
||||
#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask
|
||||
#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status
|
||||
#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status
|
||||
#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear
|
||||
#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select
|
||||
#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select
|
||||
#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select
|
||||
#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select
|
||||
#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select
|
||||
#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select
|
||||
#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select
|
||||
#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select
|
||||
#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable
|
||||
#define GPIO_O_LOCK 0x00000520 // GPIO Lock
|
||||
#define GPIO_O_CR 0x00000524 // GPIO Commit
|
||||
#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
|
||||
#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
|
||||
#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
|
||||
#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
|
||||
#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
|
||||
#define GPIO_IM_GPIO_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
|
||||
#define GPIO_RIS_GPIO_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
|
||||
#define GPIO_MIS_GPIO_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_ICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
|
||||
#define GPIO_ICR_GPIO_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_LOCK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
|
||||
#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
|
||||
// and may be modified
|
||||
#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
|
||||
// and may not be modified
|
||||
#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
|
||||
#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on
|
||||
// DustDevil-class devices and
|
||||
// later
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_SI register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the GPIO register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_O_PeriphID4 0x00000FD0
|
||||
#define GPIO_O_PeriphID5 0x00000FD4
|
||||
#define GPIO_O_PeriphID6 0x00000FD8
|
||||
#define GPIO_O_PeriphID7 0x00000FDC
|
||||
#define GPIO_O_PeriphID0 0x00000FE0
|
||||
#define GPIO_O_PeriphID1 0x00000FE4
|
||||
#define GPIO_O_PeriphID2 0x00000FE8
|
||||
#define GPIO_O_PeriphID3 0x00000FEC
|
||||
#define GPIO_O_PCellID0 0x00000FF0
|
||||
#define GPIO_O_PCellID1 0x00000FF4
|
||||
#define GPIO_O_PCellID2 0x00000FF8
|
||||
#define GPIO_O_PCellID3 0x00000FFC
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the GPIO Register reset values.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV
|
||||
#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV
|
||||
#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV
|
||||
#define GPIO_RV_PCellID1 0x000000F0
|
||||
#define GPIO_RV_PCellID3 0x000000B1
|
||||
#define GPIO_RV_PeriphID0 0x00000061
|
||||
#define GPIO_RV_PeriphID1 0x00000010
|
||||
#define GPIO_RV_PCellID0 0x0000000D
|
||||
#define GPIO_RV_PCellID2 0x00000005
|
||||
#define GPIO_RV_PeriphID2 0x00000004
|
||||
#define GPIO_RV_LOCK 0x00000001 // Lock register RV
|
||||
#define GPIO_RV_PeriphID7 0x00000000
|
||||
#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV
|
||||
#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV
|
||||
#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV
|
||||
#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV
|
||||
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV
|
||||
#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV
|
||||
#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV
|
||||
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV
|
||||
#define GPIO_RV_PeriphID4 0x00000000
|
||||
#define GPIO_RV_PeriphID5 0x00000000
|
||||
#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV
|
||||
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV
|
||||
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV
|
||||
#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV
|
||||
#define GPIO_RV_DIR 0x00000000 // Data direction reg RV
|
||||
#define GPIO_RV_PeriphID6 0x00000000
|
||||
#define GPIO_RV_PeriphID3 0x00000000
|
||||
#define GPIO_RV_DATA 0x00000000 // Data register reset value
|
||||
#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_GPIO_H__
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 10636 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_INTS_H__
|
||||
#define __HW_INTS_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the fault assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FAULT_NMI 2 // NMI fault
|
||||
#define FAULT_HARD 3 // Hard fault
|
||||
#define FAULT_MPU 4 // MPU fault
|
||||
#define FAULT_BUS 5 // Bus fault
|
||||
#define FAULT_USAGE 6 // Usage fault
|
||||
#define FAULT_SVCALL 11 // SVCall
|
||||
#define FAULT_DEBUG 12 // Debug monitor
|
||||
#define FAULT_PENDSV 14 // PendSV
|
||||
#define FAULT_SYSTICK 15 // System Tick
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the interrupt assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_GPIOA 16 // GPIO Port A
|
||||
#define INT_GPIOB 17 // GPIO Port B
|
||||
#define INT_GPIOC 18 // GPIO Port C
|
||||
#define INT_GPIOD 19 // GPIO Port D
|
||||
#define INT_GPIOE 20 // GPIO Port E
|
||||
#define INT_UART0 21 // UART0 Rx and Tx
|
||||
#define INT_UART1 22 // UART1 Rx and Tx
|
||||
#define INT_SSI0 23 // SSI0 Rx and Tx
|
||||
#define INT_I2C0 24 // I2C0 Master and Slave
|
||||
#define INT_PWM0_FAULT 25 // PWM0 Fault
|
||||
#define INT_PWM0_0 26 // PWM0 Generator 0
|
||||
#define INT_PWM0_1 27 // PWM0 Generator 1
|
||||
#define INT_PWM0_2 28 // PWM0 Generator 2
|
||||
#define INT_QEI0 29 // Quadrature Encoder 0
|
||||
#define INT_ADC0SS0 30 // ADC0 Sequence 0
|
||||
#define INT_ADC0SS1 31 // ADC0 Sequence 1
|
||||
#define INT_ADC0SS2 32 // ADC0 Sequence 2
|
||||
#define INT_ADC0SS3 33 // ADC0 Sequence 3
|
||||
#define INT_WATCHDOG 34 // Watchdog timer
|
||||
#define INT_TIMER0A 35 // Timer 0 subtimer A
|
||||
#define INT_TIMER0B 36 // Timer 0 subtimer B
|
||||
#define INT_TIMER1A 37 // Timer 1 subtimer A
|
||||
#define INT_TIMER1B 38 // Timer 1 subtimer B
|
||||
#define INT_TIMER2A 39 // Timer 2 subtimer A
|
||||
#define INT_TIMER2B 40 // Timer 2 subtimer B
|
||||
#define INT_COMP0 41 // Analog Comparator 0
|
||||
#define INT_COMP1 42 // Analog Comparator 1
|
||||
#define INT_COMP2 43 // Analog Comparator 2
|
||||
#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
|
||||
#define INT_FLASH 45 // FLASH Control
|
||||
#define INT_GPIOF 46 // GPIO Port F
|
||||
#define INT_GPIOG 47 // GPIO Port G
|
||||
#define INT_GPIOH 48 // GPIO Port H
|
||||
#define INT_UART2 49 // UART2 Rx and Tx
|
||||
#define INT_SSI1 50 // SSI1 Rx and Tx
|
||||
#define INT_TIMER3A 51 // Timer 3 subtimer A
|
||||
#define INT_TIMER3B 52 // Timer 3 subtimer B
|
||||
#define INT_I2C1 53 // I2C1 Master and Slave
|
||||
#define INT_QEI1 54 // Quadrature Encoder 1
|
||||
#define INT_CAN0 55 // CAN0
|
||||
#define INT_CAN1 56 // CAN1
|
||||
#define INT_CAN2 57 // CAN2
|
||||
#define INT_ETH 58 // Ethernet
|
||||
#define INT_HIBERNATE 59 // Hibernation module
|
||||
#define INT_USB0 60 // USB 0 Controller
|
||||
#define INT_PWM0_3 61 // PWM0 Generator 3
|
||||
#define INT_UDMA 62 // uDMA controller
|
||||
#define INT_UDMAERR 63 // uDMA Error
|
||||
#define INT_ADC1SS0 64 // ADC1 Sequence 0
|
||||
#define INT_ADC1SS1 65 // ADC1 Sequence 1
|
||||
#define INT_ADC1SS2 66 // ADC1 Sequence 2
|
||||
#define INT_ADC1SS3 67 // ADC1 Sequence 3
|
||||
#define INT_I2S0 68 // I2S0
|
||||
#define INT_EPI0 69 // EPI0
|
||||
#define INT_GPIOJ 70 // GPIO Port J
|
||||
#define INT_GPIOK 71 // GPIO Port K
|
||||
#define INT_GPIOL 72 // GPIO Port L
|
||||
#define INT_SSI2 73 // SSI2
|
||||
#define INT_SSI3 74 // SSI3
|
||||
#define INT_UART3 75 // UART3
|
||||
#define INT_UART4 76 // UART4
|
||||
#define INT_UART5 77 // UART5
|
||||
#define INT_UART6 78 // UART6
|
||||
#define INT_UART7 79 // UART7
|
||||
#define INT_I2C2 84 // I2C2
|
||||
#define INT_I2C3 85 // I2C3
|
||||
#define INT_TIMER4A 86 // Timer 4A
|
||||
#define INT_TIMER4B 87 // Timer 4B
|
||||
#define INT_TIMER5A 108 // Timer 5A
|
||||
#define INT_TIMER5B 109 // Timer 5B
|
||||
#define INT_WTIMER0A 110 // Wide Timer 0A
|
||||
#define INT_WTIMER0B 111 // Wide Timer 0B
|
||||
#define INT_WTIMER1A 112 // Wide Timer 1A
|
||||
#define INT_WTIMER1B 113 // Wide Timer 1B
|
||||
#define INT_WTIMER2A 114 // Wide Timer 2A
|
||||
#define INT_WTIMER2B 115 // Wide Timer 2B
|
||||
#define INT_WTIMER3A 116 // Wide Timer 3A
|
||||
#define INT_WTIMER3B 117 // Wide Timer 3B
|
||||
#define INT_WTIMER4A 118 // Wide Timer 4A
|
||||
#define INT_WTIMER4B 119 // Wide Timer 4B
|
||||
#define INT_WTIMER5A 120 // Wide Timer 5A
|
||||
#define INT_WTIMER5B 121 // Wide Timer 5B
|
||||
#define INT_SYSEXC 122 // System Exception (imprecise)
|
||||
#define INT_PECI0 123 // PECI 0
|
||||
#define INT_LPC0 124 // LPC 0
|
||||
#define INT_I2C4 125 // I2C4
|
||||
#define INT_I2C5 126 // I2C5
|
||||
#define INT_GPIOM 127 // GPIO Port M
|
||||
#define INT_GPION 128 // GPIO Port N
|
||||
#define INT_FAN0 130 // FAN 0
|
||||
#define INT_GPIOP0 132 // GPIO Port P (Summary or P0)
|
||||
#define INT_GPIOP1 133 // GPIO Port P1
|
||||
#define INT_GPIOP2 134 // GPIO Port P2
|
||||
#define INT_GPIOP3 135 // GPIO Port P3
|
||||
#define INT_GPIOP4 136 // GPIO Port P4
|
||||
#define INT_GPIOP5 137 // GPIO Port P5
|
||||
#define INT_GPIOP6 138 // GPIO Port P6
|
||||
#define INT_GPIOP7 139 // GPIO Port P7
|
||||
#define INT_GPIOQ0 140 // GPIO Port Q (Summary or Q0)
|
||||
#define INT_GPIOQ1 141 // GPIO Port Q1
|
||||
#define INT_GPIOQ2 142 // GPIO Port Q2
|
||||
#define INT_GPIOQ3 143 // GPIO Port Q3
|
||||
#define INT_GPIOQ4 144 // GPIO Port Q4
|
||||
#define INT_GPIOQ5 145 // GPIO Port Q5
|
||||
#define INT_GPIOQ6 146 // GPIO Port Q6
|
||||
#define INT_GPIOQ7 147 // GPIO Port Q7
|
||||
#define INT_PWM1_0 150 // PWM1 Generator 0
|
||||
#define INT_PWM1_1 151 // PWM1 Generator 1
|
||||
#define INT_PWM1_2 152 // PWM1 Generator 2
|
||||
#define INT_PWM1_3 153 // PWM1 Generator 3
|
||||
#define INT_PWM1_FAULT 154 // PWM1 Fault
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the total number of interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NUM_INTERRUPTS 155
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the total number of priority levels.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NUM_PRIORITY 8
|
||||
#define NUM_PRIORITY_BITS 3
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the interrupt assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_SSI 23 // SSI Rx and Tx
|
||||
#define INT_I2C 24 // I2C Master and Slave
|
||||
#define INT_PWM_FAULT 25 // PWM Fault
|
||||
#define INT_PWM0 26 // PWM Generator 0
|
||||
#define INT_PWM1 27 // PWM Generator 1
|
||||
#define INT_PWM2 28 // PWM Generator 2
|
||||
#define INT_QEI 29 // Quadrature Encoder
|
||||
#define INT_ADC0 30 // ADC Sequence 0
|
||||
#define INT_ADC1 31 // ADC Sequence 1
|
||||
#define INT_ADC2 32 // ADC Sequence 2
|
||||
#define INT_ADC3 33 // ADC Sequence 3
|
||||
#define INT_PWM3 61 // PWM Generator 3
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_INTS_H__
|
||||
|
|
@ -0,0 +1,167 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_memmap.h - Macros defining the memory map of Stellaris.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 10636 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_MEMMAP_H__
|
||||
#define __HW_MEMMAP_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the base address of the memories and
|
||||
// peripherals.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_BASE 0x00000000 // FLASH memory
|
||||
#define SRAM_BASE 0x20000000 // SRAM memory
|
||||
#define WATCHDOG0_BASE 0x40000000 // Watchdog0
|
||||
#define WATCHDOG1_BASE 0x40001000 // Watchdog1
|
||||
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
|
||||
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
|
||||
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
|
||||
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
|
||||
#define SSI0_BASE 0x40008000 // SSI0
|
||||
#define SSI1_BASE 0x40009000 // SSI1
|
||||
#define SSI2_BASE 0x4000A000 // SSI2
|
||||
#define SSI3_BASE 0x4000B000 // SSI3
|
||||
#define UART0_BASE 0x4000C000 // UART0
|
||||
#define UART1_BASE 0x4000D000 // UART1
|
||||
#define UART2_BASE 0x4000E000 // UART2
|
||||
#define UART3_BASE 0x4000F000 // UART3
|
||||
#define UART4_BASE 0x40010000 // UART4
|
||||
#define UART5_BASE 0x40011000 // UART5
|
||||
#define UART6_BASE 0x40012000 // UART6
|
||||
#define UART7_BASE 0x40013000 // UART7
|
||||
#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
|
||||
#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
|
||||
#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
|
||||
#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
|
||||
#define I2C2_MASTER_BASE 0x40022000 // I2C2 Master
|
||||
#define I2C2_SLAVE_BASE 0x40022800 // I2C2 Slave
|
||||
#define I2C3_MASTER_BASE 0x40023000 // I2C3 Master
|
||||
#define I2C3_SLAVE_BASE 0x40023800 // I2C3 Slave
|
||||
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
|
||||
#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
|
||||
#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
|
||||
#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
|
||||
#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM)
|
||||
#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM)
|
||||
#define QEI0_BASE 0x4002C000 // QEI0
|
||||
#define QEI1_BASE 0x4002D000 // QEI1
|
||||
#define TIMER0_BASE 0x40030000 // Timer0
|
||||
#define TIMER1_BASE 0x40031000 // Timer1
|
||||
#define TIMER2_BASE 0x40032000 // Timer2
|
||||
#define TIMER3_BASE 0x40033000 // Timer3
|
||||
#define TIMER4_BASE 0x40034000 // Timer4
|
||||
#define TIMER5_BASE 0x40035000 // Timer5
|
||||
#define WTIMER0_BASE 0x40036000 // Wide Timer0
|
||||
#define WTIMER1_BASE 0x40037000 // Wide Timer1
|
||||
#define ADC0_BASE 0x40038000 // ADC0
|
||||
#define ADC1_BASE 0x40039000 // ADC1
|
||||
#define COMP_BASE 0x4003C000 // Analog comparators
|
||||
#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
|
||||
#define CAN0_BASE 0x40040000 // CAN0
|
||||
#define CAN1_BASE 0x40041000 // CAN1
|
||||
#define CAN2_BASE 0x40042000 // CAN2
|
||||
#define ETH_BASE 0x40048000 // Ethernet
|
||||
#define MAC_BASE 0x40048000 // Ethernet
|
||||
#define WTIMER2_BASE 0x4004C000 // Wide Timer2
|
||||
#define WTIMER3_BASE 0x4004D000 // Wide Timer3
|
||||
#define WTIMER4_BASE 0x4004E000 // Wide Timer4
|
||||
#define WTIMER5_BASE 0x4004F000 // Wide Timer5
|
||||
#define USB0_BASE 0x40050000 // USB 0 Controller
|
||||
#define I2S0_BASE 0x40054000 // I2S0
|
||||
#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
|
||||
#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
|
||||
#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
|
||||
#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
|
||||
#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
|
||||
#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
|
||||
#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
|
||||
#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
|
||||
#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
|
||||
#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K
|
||||
#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L
|
||||
#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M
|
||||
#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N
|
||||
#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P
|
||||
#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q
|
||||
#define LPC0_BASE 0x40080000 // Low Pin Count Interface (LPC)
|
||||
#define FAN0_BASE 0x40084000 // Fan Control (FAN)
|
||||
#define EEPROM_BASE 0x400AF000 // EEPROM memory
|
||||
#define PECI0_BASE 0x400B0000 // Platform Environment Control
|
||||
// Interface (PECI)
|
||||
#define I2C4_MASTER_BASE 0x400C0000 // I2C4 Master
|
||||
#define I2C4_SLAVE_BASE 0x400C0800 // I2C4 Slave
|
||||
#define I2C5_MASTER_BASE 0x400C1000 // I2C5 Master
|
||||
#define I2C5_SLAVE_BASE 0x400C1800 // I2C5 Slave
|
||||
#define EPI0_BASE 0x400D0000 // EPI0
|
||||
#define SYSEXC_BASE 0x400F9000 // System Exception Module
|
||||
#define HIB_BASE 0x400FC000 // Hibernation Module
|
||||
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
|
||||
#define SYSCTL_BASE 0x400FE000 // System Control
|
||||
#define UDMA_BASE 0x400FF000 // uDMA Controller
|
||||
#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
|
||||
#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
|
||||
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
|
||||
#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
|
||||
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the base address of the memories
|
||||
// and peripherals.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WATCHDOG_BASE 0x40000000 // Watchdog
|
||||
#define SSI_BASE 0x40008000 // SSI
|
||||
#define I2C_MASTER_BASE 0x40020000 // I2C Master
|
||||
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
|
||||
#define PWM_BASE 0x40028000 // PWM
|
||||
#define QEI_BASE 0x4002C000 // QEI
|
||||
#define ADC_BASE 0x40038000 // ADC
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_MEMMAP_H__
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,212 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_types.h - Common types and macros.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 10636 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_TYPES_H__
|
||||
#define __HW_TYPES_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Define a boolean type, and values for true and false.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef unsigned char tBoolean;
|
||||
|
||||
#ifndef true
|
||||
#define true 1
|
||||
#endif
|
||||
|
||||
#ifndef false
|
||||
#define false 0
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros for hardware access, both direct and via the bit-band region.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HWREG(x) \
|
||||
(*((volatile unsigned long *)(x)))
|
||||
#define HWREGH(x) \
|
||||
(*((volatile unsigned short *)(x)))
|
||||
#define HWREGB(x) \
|
||||
(*((volatile unsigned char *)(x)))
|
||||
#define HWREGBITW(x, b) \
|
||||
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
#define HWREGBITH(x, b) \
|
||||
HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
#define HWREGBITB(x, b) \
|
||||
HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Helper Macros for determining silicon revisions, etc.
|
||||
//
|
||||
// These macros will be used by Driverlib at "run-time" to create necessary
|
||||
// conditional code blocks that will allow a single version of the Driverlib
|
||||
// "binary" code to support multiple(all) Stellaris silicon revisions.
|
||||
//
|
||||
// It is expected that these macros will be used inside of a standard 'C'
|
||||
// conditional block of code, e.g.
|
||||
//
|
||||
// if(CLASS_IS_SANDSTORM)
|
||||
// {
|
||||
// do some Sandstorm-class specific code here.
|
||||
// }
|
||||
//
|
||||
// By default, these macros will be defined as run-time checks of the
|
||||
// appropriate register(s) to allow creation of run-time conditional code
|
||||
// blocks for a common DriverLib across the entire Stellaris family.
|
||||
//
|
||||
// However, if code-space optimization is required, these macros can be "hard-
|
||||
// coded" for a specific version of Stellaris silicon. Many compilers will
|
||||
// then detect the "hard-coded" conditionals, and appropriately optimize the
|
||||
// code blocks, eliminating any "unreachable" code. This would result in
|
||||
// a smaller Driverlib, thus producing a smaller final application size, but
|
||||
// at the cost of limiting the Driverlib binary to a specific Stellaris
|
||||
// silicon revision.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef CLASS_IS_SANDSTORM
|
||||
#define CLASS_IS_SANDSTORM \
|
||||
(((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM)))
|
||||
#endif
|
||||
|
||||
#ifndef CLASS_IS_FURY
|
||||
#define CLASS_IS_FURY \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY))
|
||||
#endif
|
||||
|
||||
#ifndef CLASS_IS_DUSTDEVIL
|
||||
#define CLASS_IS_DUSTDEVIL \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL))
|
||||
#endif
|
||||
|
||||
#ifndef CLASS_IS_TEMPEST
|
||||
#define CLASS_IS_TEMPEST \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST))
|
||||
#endif
|
||||
|
||||
#ifndef CLASS_IS_FIRESTORM
|
||||
#define CLASS_IS_FIRESTORM \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FIRESTORM))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_A0
|
||||
#define REVISION_IS_A0 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_A1
|
||||
#define REVISION_IS_A1 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_A2
|
||||
#define REVISION_IS_A2 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_B0
|
||||
#define REVISION_IS_B0 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_B1
|
||||
#define REVISION_IS_B1 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C0
|
||||
#define REVISION_IS_C0 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C1
|
||||
#define REVISION_IS_C1 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C2
|
||||
#define REVISION_IS_C2 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C3
|
||||
#define REVISION_IS_C3 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_3))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C5
|
||||
#define REVISION_IS_C5 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_5))
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Deprecated silicon class and revision detection macros.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM
|
||||
#define DEVICE_IS_FURY CLASS_IS_FURY
|
||||
#define DEVICE_IS_REVA2 REVISION_IS_A2
|
||||
#define DEVICE_IS_REVC1 REVISION_IS_C1
|
||||
#define DEVICE_IS_REVC2 REVISION_IS_C2
|
||||
#endif
|
||||
|
||||
#endif // __HW_TYPES_H__
|
||||
|
|
@ -0,0 +1,522 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_uart.h - Macros and defines used when accessing the UART hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 10636 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_UART_H__
|
||||
#define __HW_UART_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the UART register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_O_DR 0x00000000 // UART Data
|
||||
#define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear
|
||||
#define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear
|
||||
#define UART_O_FR 0x00000018 // UART Flag
|
||||
#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register
|
||||
#define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor
|
||||
#define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate
|
||||
// Divisor
|
||||
#define UART_O_LCRH 0x0000002C // UART Line Control
|
||||
#define UART_O_CTL 0x00000030 // UART Control
|
||||
#define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select
|
||||
#define UART_O_IM 0x00000038 // UART Interrupt Mask
|
||||
#define UART_O_RIS 0x0000003C // UART Raw Interrupt Status
|
||||
#define UART_O_MIS 0x00000040 // UART Masked Interrupt Status
|
||||
#define UART_O_ICR 0x00000044 // UART Interrupt Clear
|
||||
#define UART_O_DMACTL 0x00000048 // UART DMA Control
|
||||
#define UART_O_LCTL 0x00000090 // UART LIN Control
|
||||
#define UART_O_LSS 0x00000094 // UART LIN Snap Shot
|
||||
#define UART_O_LTIM 0x00000098 // UART LIN Timer
|
||||
#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address
|
||||
#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask
|
||||
#define UART_O_PP 0x00000FC0 // UART Peripheral Properties
|
||||
#define UART_O_CC 0x00000FC8 // UART Clock Configuration
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_DR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_DR_OE 0x00000800 // UART Overrun Error
|
||||
#define UART_DR_BE 0x00000400 // UART Break Error
|
||||
#define UART_DR_PE 0x00000200 // UART Parity Error
|
||||
#define UART_DR_FE 0x00000100 // UART Framing Error
|
||||
#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
|
||||
#define UART_DR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_RSR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_RSR_OE 0x00000008 // UART Overrun Error
|
||||
#define UART_RSR_BE 0x00000004 // UART Break Error
|
||||
#define UART_RSR_PE 0x00000002 // UART Parity Error
|
||||
#define UART_RSR_FE 0x00000001 // UART Framing Error
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_ECR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_ECR_DATA_M 0x000000FF // Error Clear
|
||||
#define UART_ECR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_FR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FR_RI 0x00000100 // Ring Indicator
|
||||
#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
|
||||
#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
|
||||
#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
|
||||
#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
|
||||
#define UART_FR_BUSY 0x00000008 // UART Busy
|
||||
#define UART_FR_DCD 0x00000004 // Data Carrier Detect
|
||||
#define UART_FR_DSR 0x00000002 // Data Set Ready
|
||||
#define UART_FR_CTS 0x00000001 // Clear To Send
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_ILPR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
|
||||
#define UART_ILPR_ILPDVSR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_IBRD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
|
||||
#define UART_IBRD_DIVINT_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_FBRD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
|
||||
#define UART_FBRD_DIVFRAC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_LCRH register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
|
||||
#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
|
||||
#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
|
||||
#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
|
||||
#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
|
||||
#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
|
||||
#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
|
||||
#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
|
||||
#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
|
||||
#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
|
||||
#define UART_LCRH_BRK 0x00000001 // UART Send Break
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
|
||||
#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
|
||||
#define UART_CTL_RTS 0x00000800 // Request to Send
|
||||
#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
|
||||
#define UART_CTL_RXE 0x00000200 // UART Receive Enable
|
||||
#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
|
||||
#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
|
||||
#define UART_CTL_LIN 0x00000040 // LIN Mode Enable
|
||||
#define UART_CTL_HSE 0x00000020 // High-Speed Enable
|
||||
#define UART_CTL_EOT 0x00000010 // End of Transmission
|
||||
#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
|
||||
#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
|
||||
#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
|
||||
#define UART_CTL_UARTEN 0x00000001 // UART Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_IFLS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
|
||||
// Level Select
|
||||
#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
|
||||
#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full
|
||||
#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
|
||||
#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full
|
||||
#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full
|
||||
#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
|
||||
// Level Select
|
||||
#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
|
||||
#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full
|
||||
#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
|
||||
#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full
|
||||
#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask
|
||||
#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
|
||||
#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
|
||||
// Mask
|
||||
#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
|
||||
#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
|
||||
// Mask
|
||||
#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
|
||||
#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
|
||||
#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
|
||||
// Mask
|
||||
#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
|
||||
// Mask
|
||||
#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
|
||||
#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
|
||||
#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
|
||||
// Interrupt Mask
|
||||
#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
|
||||
// Interrupt Mask
|
||||
#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
|
||||
// Interrupt Mask
|
||||
#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
|
||||
// Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
|
||||
// Status
|
||||
#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
|
||||
// Status
|
||||
#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
|
||||
// Interrupt Status
|
||||
#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
|
||||
#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
|
||||
// Status
|
||||
#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
|
||||
// Status
|
||||
#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
|
||||
// Status
|
||||
#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
|
||||
// Status
|
||||
#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
|
||||
// Interrupt Status
|
||||
#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
|
||||
// Status
|
||||
#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
|
||||
// Status
|
||||
#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
|
||||
// Interrupt Status
|
||||
#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
|
||||
// Raw Interrupt Status
|
||||
#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
|
||||
// Interrupt Status
|
||||
#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
|
||||
// Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
|
||||
// Status
|
||||
#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
|
||||
// Status
|
||||
#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
|
||||
// Status
|
||||
#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
|
||||
// Status
|
||||
#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
|
||||
// Status
|
||||
#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
|
||||
// Masked Interrupt Status
|
||||
#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
|
||||
// Interrupt Status
|
||||
#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
|
||||
// Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_ICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_ICR_LME5IC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
|
||||
#define UART_ICR_LME1IC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
|
||||
#define UART_ICR_LMSBIC 0x00002000 // LIN Mode Sync Break Interrupt
|
||||
// Clear
|
||||
#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
|
||||
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
|
||||
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
|
||||
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
|
||||
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
|
||||
#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
|
||||
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
|
||||
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
|
||||
#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
|
||||
// Interrupt Clear
|
||||
#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
|
||||
// Interrupt Clear
|
||||
#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
|
||||
// Interrupt Clear
|
||||
#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
|
||||
// Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_DMACTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
|
||||
#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
|
||||
#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_LCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length
|
||||
#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits
|
||||
// (default)
|
||||
#define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits
|
||||
#define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits
|
||||
#define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits
|
||||
#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_LSS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot
|
||||
#define UART_LSS_TSS_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_LTIM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
|
||||
#define UART_LTIM_TIMER_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_9BITADDR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode
|
||||
#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode
|
||||
#define UART_9BITADDR_ADDR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_9BITAMASK
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode
|
||||
#define UART_9BITAMASK_MASK_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_PP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_PP_NB 0x00000002 // 9-Bit Support
|
||||
#define UART_PP_SC 0x00000001 // Smart Card Support
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the UART_O_CC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
|
||||
#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default)
|
||||
#define UART_CC_CS_PIOSC 0x00000005 // PIOSC
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the UART register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
|
||||
#define UART_O_PeriphID4 0x00000FD0
|
||||
#define UART_O_PeriphID5 0x00000FD4
|
||||
#define UART_O_PeriphID6 0x00000FD8
|
||||
#define UART_O_PeriphID7 0x00000FDC
|
||||
#define UART_O_PeriphID0 0x00000FE0
|
||||
#define UART_O_PeriphID1 0x00000FE4
|
||||
#define UART_O_PeriphID2 0x00000FE8
|
||||
#define UART_O_PeriphID3 0x00000FEC
|
||||
#define UART_O_PCellID0 0x00000FF0
|
||||
#define UART_O_PCellID1 0x00000FF4
|
||||
#define UART_O_PCellID2 0x00000FF8
|
||||
#define UART_O_PCellID3 0x00000FFC
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the UART_O_DR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_DR_DATA_MASK 0x000000FF // UART data
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the UART_O_IBRD
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the UART_O_FBRD
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the UART_O_LCR_H
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select
|
||||
#define UART_LCR_H_WLEN 0x00000060 // Word length
|
||||
#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data
|
||||
#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data
|
||||
#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data
|
||||
#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data
|
||||
#define UART_LCR_H_FEN 0x00000010 // Enable FIFO
|
||||
#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select
|
||||
#define UART_LCR_H_EPS 0x00000004 // Even Parity Select
|
||||
#define UART_LCR_H_PEN 0x00000002 // Parity Enable
|
||||
#define UART_LCR_H_BRK 0x00000001 // Send Break
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the UART_O_IFLS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask
|
||||
#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the UART_O_ICR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
|
||||
#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
|
||||
#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
|
||||
// Clear
|
||||
#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
|
||||
UART_RSR_FE)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the Reset Values for UART
|
||||
// Registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_RV_CTL 0x00000300
|
||||
#define UART_RV_PCellID1 0x000000F0
|
||||
#define UART_RV_PCellID3 0x000000B1
|
||||
#define UART_RV_FR 0x00000090
|
||||
#define UART_RV_PeriphID2 0x00000018
|
||||
#define UART_RV_IFLS 0x00000012
|
||||
#define UART_RV_PeriphID0 0x00000011
|
||||
#define UART_RV_PCellID0 0x0000000D
|
||||
#define UART_RV_PCellID2 0x00000005
|
||||
#define UART_RV_PeriphID3 0x00000001
|
||||
#define UART_RV_PeriphID4 0x00000000
|
||||
#define UART_RV_LCR_H 0x00000000
|
||||
#define UART_RV_PeriphID6 0x00000000
|
||||
#define UART_RV_DR 0x00000000
|
||||
#define UART_RV_RSR 0x00000000
|
||||
#define UART_RV_ECR 0x00000000
|
||||
#define UART_RV_PeriphID5 0x00000000
|
||||
#define UART_RV_RIS 0x00000000
|
||||
#define UART_RV_FBRD 0x00000000
|
||||
#define UART_RV_IM 0x00000000
|
||||
#define UART_RV_MIS 0x00000000
|
||||
#define UART_RV_ICR 0x00000000
|
||||
#define UART_RV_PeriphID1 0x00000000
|
||||
#define UART_RV_PeriphID7 0x00000000
|
||||
#define UART_RV_IBRD 0x00000000
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_UART_H__
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,3 @@
|
|||
SRC_DIR := Libraries
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -26,6 +26,7 @@ endif
|
|||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/stm32f407-st-discovery)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(KERNEL_ROOT)/arch/arm/cortex-m4 \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/sdio \
|
||||
-I$(BSP_ROOT)/include \
|
||||
|
|
@ -37,6 +38,7 @@ endif
|
|||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/aiit-arm32-board)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(KERNEL_ROOT)/arch/arm/cortex-m4 \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/include \
|
||||
|
|
@ -52,6 +54,7 @@ endif
|
|||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/stm32f407zgt6)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(KERNEL_ROOT)/arch/arm/cortex-m4 \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/sdio\
|
||||
-I$(BSP_ROOT)/include \
|
||||
|
|
@ -109,6 +112,17 @@ KERNELPATHS :=-I$(BSP_ROOT) \
|
|||
-I$(KERNEL_ROOT)/include #
|
||||
endif
|
||||
|
||||
ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/cortex-m3-emulator)
|
||||
KERNELPATHS :=-I$(BSP_ROOT) \
|
||||
-I$(KERNEL_ROOT)/arch/arm/cortex-m3 \
|
||||
-I$(BSP_ROOT)/third_party_driver \
|
||||
-I$(BSP_ROOT)/third_party_driver/Libraries/driverlib \
|
||||
-I$(BSP_ROOT)/third_party_driver/Libraries/ \
|
||||
-I$(BSP_ROOT)/third_party_driver/Libraries/inc \
|
||||
-I$(KERNEL_ROOT)/include \
|
||||
-I$(BSP_ROOT)/include #
|
||||
endif
|
||||
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/arch \
|
||||
-I$(KERNEL_ROOT)/arch/risc-v/shared/kernel_service #
|
||||
|
||||
|
|
@ -147,7 +161,6 @@ KERNELPATHS +=-I$(KERNEL_ROOT)/tool/shell/letter-shell \
|
|||
endif
|
||||
|
||||
|
||||
|
||||
ifeq ($(CONFIG_LIB_NEWLIB),y)
|
||||
KERNELPATHS += -I$(KERNEL_ROOT)/lib/newlib/include #
|
||||
endif
|
||||
|
|
@ -166,7 +179,6 @@ endif
|
|||
|
||||
ifeq ($(ARCH), arm)
|
||||
KERNELPATHS +=-I$(KERNEL_ROOT)/arch/arm/shared \
|
||||
-I$(KERNEL_ROOT)/arch/arm/cortex-m4 \
|
||||
-I$(KERNEL_ROOT)/lib/comlibc/common #
|
||||
endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue