forked from opendacs/PyHCL
850 lines
25 KiB
Python
850 lines
25 KiB
Python
from __future__ import annotations
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from abc import ABC
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from dataclasses import dataclass, field
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from typing import Dict, List, Optional
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from pyhcl.ir.low_node import FirrtlNode
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from pyhcl.ir.low_prim import PrimOp, Bits, Cat
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from pyhcl.ir.utils import backspace, indent, deleblankline, backspace1, get_binary_width, TransformException, DAG
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class Info(FirrtlNode, ABC):
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"""INFOs"""
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def serialize(self) -> str:
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"""default implementation"""
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return self.__repr__()
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def verilog_serialize(self) -> str:
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return self.__repr__()
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class NoInfo(Info):
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def serialize(self) -> str:
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return ""
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def verilog_serialize(self) -> str:
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return ""
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@dataclass(frozen=True)
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class FileInfo(Info):
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info: StringLit
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def serialize(self) -> str:
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return f"@[{self.info.serialize()}]"
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def verilog_serialize(self) -> str:
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return f" /*[{self.info.verilog_serialize()}]*/"
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@dataclass(frozen=True)
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class StringLit(FirrtlNode):
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"""Utility Literal Representation"""
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string: str
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def escape(self) -> str:
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return repr(self.string).replace('"', '\\"')
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def serialize(self) -> str:
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return self.escape()[1:-1]
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def verilog_serialize(self) -> str:
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return self.serialize()
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class Expression(FirrtlNode, ABC):
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"""EXPRESSIONs"""
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...
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class Type(FirrtlNode, ABC):
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"""TYPEs"""
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def map_type(self, typ):
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...
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def map_width(self, typ):
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...
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@dataclass(frozen=True, init=False)
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class UnknownType(Type):
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def serialize(self) -> str:
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return '?'
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def verilog_serialize(self) -> str:
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return self.serialize()
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@dataclass(frozen=True)
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class Reference(Expression):
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name: str
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typ: Type
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def serialize(self) -> str:
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return self.name
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def verilog_serialize(self) -> str:
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return self.serialize()
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@dataclass(frozen=True)
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class SubField(Expression):
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expr: Expression
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name: str
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typ: Type
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def serialize(self) -> str:
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return f"{self.expr.serialize()}.{self.name}"
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def verilog_serialize(self) -> str:
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return self.serialize()
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@dataclass(frozen=True)
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class SubIndex(Expression):
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name: str
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expr: Expression
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value: int
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typ: Type
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def serialize(self) -> str:
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return f"{self.expr.serialize()}[{self.value}]"
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def verilog_serialize(self) -> str:
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return self.serialize()
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@dataclass(frozen=True)
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class SubAccess(Expression):
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expr: Expression
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index: Expression
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typ: Type
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def serialize(self) -> str:
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return f"{self.expr.serialize()}[{self.index.serialize()}]"
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def verilog_serialize(self):
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return self.serialize()
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@dataclass(frozen=True)
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class Mux(Expression):
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cond: Expression
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tval: Expression
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fval: Expression
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typ: Type
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def serialize(self) -> str:
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return f"mux({self.cond.serialize()}, {self.tval.serialize()}, {self.fval.serialize()})"
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def verilog_serialize(self) -> str:
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return f"{self.cond.verilog_serialize()} ? {self.tval.verilog_serialize()} : {self.fval.verilog_serialize()}"
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@dataclass(frozen=True)
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class ValidIf(Expression):
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cond: Expression
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value: Expression
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typ: Type
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def serialize(self) -> str:
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return f"validif({self.cond.serialize()}, {self.value.serialize()})"
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def verilog_serialize(self) -> str:
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return f"{self.cond.verilog_serialize()} ? {self.value.verilog_serialize()} : Z"
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@dataclass(frozen=True)
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class DoPrim(Expression):
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op: PrimOp
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args: List[Expression]
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consts: List[int]
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typ: Type
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def serialize(self) -> str:
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sl: List[str] = [arg.serialize() for arg in self.args] + [repr(con) for con in self.consts]
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return f'{self.op.serialize()}({", ".join(sl)})'
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def verilog_serialize(self) -> str:
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sl: List[str] = [arg.verilog_serialize() for arg in self.args] + [repr(con) for con in self.consts]
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if isinstance(self.op, Cat):
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return f'{{{", ".join(sl)}}}'
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elif isinstance(self.op, Bits):
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arg = self.args[0]
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msb, lsb = self.consts[0], self.consts[1]
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msb_lsb = f'{msb}: {lsb}' if msb != lsb else f'{msb}'
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return f'{arg.verilog_serialize()}[{msb_lsb}]'
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if len(sl) > 1:
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return f'{self.op.verilog_serialize().join(sl)}'
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else:
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return f'{self.op.verilog_serialize()}{sl.pop()}'
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@dataclass(frozen=True)
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class Width(FirrtlNode, ABC):
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"""WIDTH"""
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@dataclass(frozen=True)
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class IntWidth(Width):
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width: int
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def serialize(self) -> str:
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return f'<{self.width}>'
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def verilog_serialize(self) -> str:
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return f'[{self.width - 1}:0]' if self.width - 1 else ""
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def verilog_literal_serialize(self) -> str:
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return str(self.width)
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@dataclass(frozen=True, init=False)
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class UnknownWidth(Width):
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width: int = None
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def serialize(self) -> str:
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return ''
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def verilog_serialize(self) -> str:
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return ''
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@dataclass(frozen=True, init=False)
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class UIntLiteral(Expression):
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value: int
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width: Width = UnknownWidth()
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@property
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def typ(self) -> Type:
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return UIntType(self.width)
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def __init__(self, value: int, width: Optional[Width] = None):
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object.__setattr__(self, 'value', value)
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iwidth = width if width is not None else IntWidth(max(value.bit_length(), 1))
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object.__setattr__(self, 'width', iwidth)
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def serialize(self) -> str:
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return f'UInt{self.width.serialize()}("h{hex(self.value)[2:]}")'
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def verilog_serialize(self) -> str:
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return f'{self.width.verilog_literal_serialize()}\'h{hex(self.value)[2:]}'
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@dataclass(frozen=True, init=False)
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class SIntLiteral(Expression):
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value: int
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width: Width = UnknownWidth()
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@property
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def typ(self) -> Type:
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return SIntType(self.width)
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def __init__(self, value: int, width: Optional[Width] = None):
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object.__setattr__(self, 'value', value)
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iwidth = width if width is not None else IntWidth(value.bit_length() + 1)
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object.__setattr__(self, 'width', iwidth)
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def serialize(self) -> str:
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return f'SInt{self.width.serialize()}("h{hex(self.value)[2:]}")'
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def verilog_serialize(self) -> str:
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return f'{self.width}\'h{hex(self.value)}'
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class GroundType(Type, ABC):
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...
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class AggregateType(Type, ABC):
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...
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@dataclass(frozen=True)
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class UIntType(GroundType):
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width: Width = UnknownWidth()
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def serialize(self) -> str:
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return f'UInt{self.width.serialize()}'
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def verilog_serialize(self) -> str:
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return f'{self.width.verilog_serialize()}'
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def irWithIndex(self, index):
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if isinstance(index, slice):
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length = index.start - index.stop + 1
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return lambda _: {"ir": DoPrim(Bits(), [_], [index.start, index.stop], UIntType(IntWidth(length))),
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"inNode": True}
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else:
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return lambda _: {"ir": DoPrim(Bits(), [_], [index, index], UIntType(IntWidth(1))),
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"inNode": True}
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@dataclass(frozen=True)
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class SIntType(GroundType):
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width: Width = UnknownWidth()
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def irWithIndex(self, index):
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if isinstance(index, slice):
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length = index.start - index.stop + 1
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return lambda _: {"ir": DoPrim(Bits(), [_], [index.start, index.stop], UIntType(IntWidth(length))),
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"inNode": True}
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else:
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return lambda _: {"ir": DoPrim(Bits(), [_], [index, index], UIntType(IntWidth(1))),
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"inNode": True}
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def serialize(self) -> str:
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return f'SInt{self.width.serialize()}'
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def verilog_serialize(self) -> str:
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return f'{self.width.serialize()}'
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class Orientation(FirrtlNode, ABC):
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"""# Orientation of [[Field]]"""
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...
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@dataclass(frozen=True, init=False)
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class Default(Orientation):
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def serialize(self) -> str:
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return ''
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def verilog_serialize(self) -> str:
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return ''
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@dataclass(frozen=True, init=False)
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class Flip(Orientation):
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def serialize(self) -> str:
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return 'flip '
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def verilog_serialize(self) -> str:
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return ''
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@dataclass(frozen=True)
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class Field(FirrtlNode):
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"""# Field of [[BundleType]]"""
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name: str
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flip: Orientation
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typ: Type
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def serialize(self) -> str:
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return f'{self.flip.serialize()}{self.name} : {self.typ.serialize()}'
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def verilog_serialize(self) -> str:
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return ''
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@dataclass(frozen=True)
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class BundleType(AggregateType):
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fields: List[Field]
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def serialize(self) -> str:
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return '{' + ', '.join([f.serialize() for f in self.fields]) + '}'
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def verilog_serialize(self) -> list:
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return ''
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@dataclass(frozen=True)
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class VectorType(AggregateType):
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typ: Type
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size: int
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def serialize(self) -> str:
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return f'{self.typ.serialize()}[{self.size}]'
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def verilog_serialize(self):
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return ''
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def irWithIndex(self, index):
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if isinstance(index, int):
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return lambda _: {"ir": SubIndex('', _, index, self.typ)}
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else:
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return lambda _: {"ir": SubAccess(_, index, self.typ)}
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@dataclass(frozen=True)
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class MemoryType(AggregateType):
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typ: Type
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size: int
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def serialize(self) -> str:
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return f'{self.typ.serialize()}[{self.size}]'
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def verilog_serialize(self) -> str:
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return f'reg {self.typ.verilog_serialize()} m [0:{self.size-1}];'
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def irWithIndex(self, index):
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return lambda _: {"ir": lambda name, mem, clk, rw: DefMemPort(name, mem, index, clk, rw), "inPort": True}
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@dataclass(frozen=True, init=False)
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class ClockType(GroundType):
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width: Width = IntWidth(1)
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def serialize(self) -> str:
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return 'Clock'
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def verilog_serialize(self) -> str:
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return ''
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@dataclass(frozen=True, init=False)
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class ResetType(GroundType):
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width: Width = IntWidth(1)
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def serialize(self) -> str:
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return "UInt<1>"
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def verilog_serialize(self) -> str:
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return ''
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@dataclass(frozen=True, init=False)
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class AsyncResetType(GroundType):
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width: Width = IntWidth(1)
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def serialize(self) -> str:
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return "AsyncReset"
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def verilog_serialize(self) -> str:
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return ''
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class Direction(FirrtlNode, ABC):
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"""[[Port]] Direction"""
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...
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@dataclass(frozen=True, init=False)
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class Input(Direction):
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def serialize(self) -> str:
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return 'input'
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def verilog_serialize(self, flip=False) -> str:
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if flip is True:
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return 'output'
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return 'input'
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@dataclass(frozen=True, init=False)
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class Output(Direction):
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def serialize(self) -> str:
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return 'output'
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def verilog_serialize(self, flip=False) -> str:
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if flip is True:
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return 'input'
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return 'output'
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# [[DefModule]] Port
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@dataclass(frozen=True)
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class Port(FirrtlNode):
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name: str
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direction: Direction
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typ: Type
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info: Info = NoInfo()
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def serialize(self) -> str:
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return f'{self.direction.serialize()} {self.name} : {self.typ.serialize()}{self.info.serialize()}'
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def verilog_serialize(self) -> str:
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return f'{self.direction.verilog_serialize()}\t{self.typ.verilog_serialize()}\t{self.name},\t{self.info.verilog_serialize()}'
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class Statement(FirrtlNode, ABC):
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...
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@dataclass(frozen=True, init=False)
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class EmptyStmt(Statement):
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def serialize(self) -> str:
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return 'skip'
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def verilog_serialize(self) -> str:
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return ''
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@dataclass(frozen=True)
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class DefWire(Statement):
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name: str
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typ: Type
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info: Info = NoInfo()
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def serialize(self) -> str:
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return f'wire {self.name} : {self.typ.serialize()}{self.info.serialize()}'
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def verilog_serialize(self) -> str:
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return f'wire\t{self.typ.verilog_serialize()}\t{self.name};\t{self.info.verilog_serialize()}'
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@dataclass(frozen=True)
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class DefRegister(Statement):
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name: str
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typ: Type
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clock: Expression
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reset: Optional[Expression] = None
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init: Optional[Expression] = None
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info: Info = NoInfo()
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def serialize(self) -> str:
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if self.init:
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i: str = indent(f' with : \nreset => ({self.reset.serialize()}, {self.init.serialize()})') \
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if self.init is not None else ""
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else:
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i: str = indent(f' with : \nreset => ({self.reset.serialize()})') \
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if self.reset is not None else ""
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return f'reg {self.name} : {self.typ.serialize()}, {self.clock.serialize()}{i}{self.info.serialize()}'
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def verilog_serialize(self) -> str:
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return f'reg\t{self.typ.verilog_serialize()}\t{self.name};\t{self.info.verilog_serialize()}'
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@dataclass(frozen=True)
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class DefInstance(Statement):
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name: str
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module: str
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ports: List[Port]
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info: Info = NoInfo()
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def serialize(self) -> str:
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return f'inst {self.name} of {self.module}{self.info.serialize()}'
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def verilog_serialize(self) -> str:
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instdeclares: List[str] = []
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portdeclares: List[str] = []
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for p in self.ports:
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portdeclares.append(f'wire\t{p.typ.verilog_serialize()}\t{self.name}_{p.name};')
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instdeclares.append(indent(f'\n.{p.name}({self.name}_{p.name}),'))
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port_decs = '\n'.join(portdeclares)
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return f"{port_decs}\n{self.module}\t{self.name}(\t{self.info.verilog_serialize()}{''.join(instdeclares)});"
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@dataclass(frozen=True)
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class WDefMemory(Statement):
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name: str
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memType: MemoryType
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dataType: Type
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depth: int
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writeLatency: int
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readLatency: int
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readers: List[str]
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writers: List[str]
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readUnderWrite: Optional[str] = None
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info: Info = NoInfo()
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def serialize(self) -> str:
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lst = [f"\ndata-type => {self.dataType.serialize()}",
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f"depth => {self.depth}",
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f"read-latency => {self.readLatency}",
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f"write-latency => {self.writeLatency}"] + \
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[f"reader => {r}" for r in self.readers] + \
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[f"writer => {w}" for w in self.writers] + \
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['read-under-write => undefined']
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s = indent('\n'.join(lst))
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return f'mem {self.name} :{self.info.serialize()}{s}'
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def verilog_serialize(self) -> str:
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return self.memType.verilog_serialize()
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@dataclass(frozen=True)
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class DefMemory(Statement):
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name: str
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memType: MemoryType
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info: Info = NoInfo()
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def serialize(self) -> str:
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return f'cmem {self.name} : {self.memType.serialize()}{self.info.serialize()}'
|
|
|
|
def verilog_serialize(self) -> str:
|
|
return f'{self.memType.verilog_serialize()}\t{self.info.verilog_serialize()}'
|
|
|
|
|
|
@dataclass(frozen=True)
|
|
class DefNode(Statement):
|
|
name: str
|
|
value: Expression
|
|
info: Info = NoInfo()
|
|
|
|
def serialize(self) -> str:
|
|
return f'node {self.name} = {self.value.serialize()}{self.info.serialize()}'
|
|
|
|
def verilog_serialize(self) -> str:
|
|
return f'wire\t{self.value.typ.verilog_serialize()}\t{self.name} = {self.value.verilog_serialize()};\t{self.info.verilog_serialize()}'
|
|
|
|
|
|
@dataclass(frozen=True)
|
|
class DefMemPort(Statement):
|
|
name: str
|
|
mem: Reference
|
|
index: Expression
|
|
clk: Expression
|
|
rw: bool
|
|
info: Info = NoInfo()
|
|
|
|
def serialize(self) -> str:
|
|
rw = "read" if self.rw else "write"
|
|
return f'{rw} mport {self.name} = {self.mem.serialize()}[{self.index.serialize()}], ' \
|
|
f'{self.clk.serialize()}{self.info.serialize()}'
|
|
|
|
def verilog_serialize(self) -> str:
|
|
memportdeclares = ''
|
|
memportdeclares += f'wire {self.mem.typ.typ.verilog_serialize()} {self.mem.verilog_serialize()}_{self.name}_data;\n'
|
|
memportdeclares += f'wire [{get_binary_width(self.mem.typ.size)-1}:0] {self.mem.verilog_serialize()}_{self.name}_addr;\n'
|
|
memportdeclares += f'wire {self.mem.verilog_serialize()}_{self.name}_en;\n'
|
|
memportdeclares += f'assign {self.mem.verilog_serialize()}_{self.name}_addr = {get_binary_width(self.mem.typ.size)}\'h{self.index.value};\n'
|
|
memportdeclares += f'assign {self.mem.verilog_serialize()}_{self.name}_en = 1\'h1;\n'
|
|
if self.rw is False:
|
|
memportdeclares += f'wire {self.mem.verilog_serialize()}_{self.name}_mask;\n'
|
|
return memportdeclares
|
|
|
|
@dataclass(frozen=False)
|
|
class Conditionally(Statement):
|
|
pred: Expression
|
|
conseq: Statement
|
|
alt: Statement
|
|
info: Info = NoInfo()
|
|
|
|
def serialize(self) -> str:
|
|
s = indent(f'\n{self.conseq.serialize()}') + \
|
|
('' if self.alt == EmptyStmt() else '\nelse :' + indent(f'\n{self.alt.serialize()}'))
|
|
return f'when {self.pred.serialize()} :{self.info.serialize()}{s}'
|
|
|
|
|
|
def verilog_serialize(self) -> str:
|
|
s = indent(f"\n{self.conseq.verilog_serialize()}") + "\nend" + \
|
|
("" if self.alt == EmptyStmt() else "\nelse begin" + indent(f"\n{self.alt.verilog_serialize()}") + "\nend")
|
|
return f"if ({self.pred.verilog_serialize()}) begin\t{self.info.verilog_serialize()}{s}"
|
|
|
|
@dataclass(frozen=True)
|
|
class Block(Statement):
|
|
stmts: List[Statement]
|
|
|
|
def serialize(self) -> str:
|
|
return '\n'.join([stmt.serialize() for stmt in self.stmts]) if self.stmts else ""
|
|
|
|
def verilog_serialize(self) -> str:
|
|
CheckCombLoop.run(self)
|
|
return '\n'.join([stmt.verilog_serialize() for stmt in self.stmts])
|
|
|
|
@dataclass(frozen=True)
|
|
class AlwaysBlock(Statement):
|
|
stmts: List[Statement]
|
|
clk: Expression = None
|
|
|
|
def serialize(self) -> str:
|
|
pass
|
|
|
|
def verilog_serialize(self) -> str:
|
|
cat_table: List[str] = []
|
|
for stmt in self.stmts:
|
|
cat_table.append(stmt.verilog_serialize())
|
|
|
|
if self.clk is None:
|
|
declares = '\n' + "\n".join(cat_table)
|
|
return deleblankline(f"always @(posedge clock) begin\n{indent(declares)}"+ "\nend")
|
|
else:
|
|
declares = '\n' + "\n".join(cat_table)
|
|
return deleblankline(f"always @(posedge {self.clk.verilog_serialize()}) begin\n{indent(declares)}" + "\nend")
|
|
|
|
@dataclass(frozen=False)
|
|
class Connect(Statement):
|
|
loc: Expression
|
|
expr: Expression
|
|
info: Info = NoInfo()
|
|
blocking: bool = True
|
|
bidirection: bool = False
|
|
mem: Dict = field(default_factory=dict)
|
|
|
|
def serialize(self) -> str:
|
|
if not self.bidirection:
|
|
return f'{self.info.serialize()}{self.loc.serialize()} <= {self.expr.serialize()}'
|
|
else:
|
|
return f'{self.info.serialize()}\n{self.loc.serialize()} <= {self.expr.serialize()}\n' + \
|
|
f'{self.info.serialize()}\n{self.expr.serialize()} <= {self.loc.serialize()}'
|
|
|
|
def verilog_serialize(self) -> str:
|
|
op = "=" if self.blocking else "<="
|
|
if self.blocking is False:
|
|
return f'{self.loc.verilog_serialize()} {op} {self.expr.verilog_serialize()};\t{self.info.verilog_serialize()}'
|
|
return f'assign\t{self.loc.verilog_serialize()} {op} {self.expr.verilog_serialize()};\t{self.info.verilog_serialize()}'
|
|
|
|
|
|
# Verification
|
|
class Verification(FirrtlNode, ABC):
|
|
pass
|
|
|
|
|
|
@dataclass(frozen=True)
|
|
class Assert(Verification):
|
|
clk: Expression
|
|
pred: Expression
|
|
en: Expression
|
|
msg: str
|
|
|
|
def serialize(self) -> str:
|
|
return f'assert({self.clk.serialize()}, {self.pred.serialize()}, {self.en.serialize()}, \"{self.msg}\")\n'
|
|
|
|
def verilog_serialize(self) -> str:
|
|
return ""
|
|
|
|
|
|
@dataclass(frozen=True)
|
|
class Assume(Verification):
|
|
clk: Expression
|
|
pred: Expression
|
|
en: Expression
|
|
msg: str
|
|
|
|
def serialize(self) -> str:
|
|
return f'assert({self.clk.serialize()}, {self.pred.serialize()}, {self.en.serialize()},{self.msg})\n'
|
|
|
|
def verilog_serialize(self) -> str:
|
|
return ""
|
|
|
|
|
|
@dataclass(frozen=True)
|
|
class Cover(Verification):
|
|
clk: Expression
|
|
pred: Expression
|
|
en: Expression
|
|
msg: str
|
|
|
|
def serialize(self) -> str:
|
|
return f'assert({self.clk.serialize()}, {self.pred.serialize()}, {self.en.serialize()},{self.msg})\n'
|
|
|
|
def verilog_serialize(self) -> str:
|
|
return ""
|
|
|
|
|
|
# Base class for modules
|
|
class DefModule(FirrtlNode, ABC):
|
|
def serializeHeader(self, typ: str) -> str:
|
|
moduledeclares = indent(''.join([f'\n{p.serialize()}' for p in self.ports]))
|
|
return f'{typ} {self.name} :{self.info.serialize()}{moduledeclares}\n'
|
|
|
|
def verilog_serializeHeader(self, typ: str) -> str:
|
|
port_declares: List[str] = []
|
|
for p in self.ports:
|
|
port_declares.append(indent("\n"+ p.verilog_serialize()))
|
|
return f"{typ} {self.name}(\t{self.info.verilog_serialize()}{''.join(port_declares)}\n);\n"
|
|
|
|
|
|
@dataclass(frozen=True)
|
|
class Module(DefModule):
|
|
name: str
|
|
ports: List[Port]
|
|
body: Statement
|
|
typ: BundleType
|
|
info: Info = NoInfo()
|
|
|
|
def serialize(self) -> str:
|
|
return self.serializeHeader('module') + indent(f'\n{self.body.serialize()}')
|
|
|
|
def verilog_serialize(self) -> str:
|
|
return self.verilog_serializeHeader('module') + indent(f'\n{self.body.verilog_serialize()}') + '\nendmodule'
|
|
|
|
|
|
@dataclass(frozen=True)
|
|
class ExtModule(DefModule):
|
|
name: str
|
|
ports: List[Port]
|
|
defname: str
|
|
typ: BundleType
|
|
info: Info = NoInfo()
|
|
|
|
def serialize(self) -> str:
|
|
s = indent(f'\ndefname = {self.defname}\n')
|
|
return f'{self.serializeHeader("extmodule")}{s}'
|
|
|
|
def verilog_serialize(self) -> str:
|
|
return ""
|
|
|
|
|
|
@dataclass(frozen=True)
|
|
class Circuit(FirrtlNode):
|
|
modules: List[DefModule]
|
|
main: str
|
|
info: Info = NoInfo()
|
|
|
|
def serialize(self) -> str:
|
|
CheckCombLoop()
|
|
ms = '\n'.join([indent(f'\n{m.serialize()}') for m in self.modules])
|
|
return f'circuit {self.main} :{self.info.serialize()}{ms}\n'
|
|
|
|
def verilog_serialize(self) -> str:
|
|
self.requires()
|
|
ms = ''.join([f'{m.verilog_serialize()}\n' for m in self.modules])
|
|
return ms
|
|
|
|
def requires(self):
|
|
CheckCombLoop()
|
|
|
|
class CheckCombLoop:
|
|
connect_graph = DAG()
|
|
reg_map = {}
|
|
|
|
@staticmethod
|
|
def run(stmt: Statement):
|
|
def check_comb_loop_e(u: Expression, v: Expression):
|
|
if isinstance(u, (Reference, SubField, SubIndex, SubAccess)):
|
|
ux, vx = u.serialize(), v.serialize()
|
|
if ux in CheckCombLoop.reg_map or vx in CheckCombLoop.reg_map:
|
|
return
|
|
try:
|
|
CheckCombLoop.connect_graph.add_node_if_not_exists(vx)
|
|
CheckCombLoop.connect_graph.add_node_if_not_exists(ux)
|
|
CheckCombLoop.connect_graph.add_edge(ux, vx)
|
|
except TransformException as e:
|
|
raise e
|
|
elif isinstance(u, Mux):
|
|
check_comb_loop_e(u.tval, v)
|
|
check_comb_loop_e(u.fval, v)
|
|
elif isinstance(u, ValidIf):
|
|
check_comb_loop_e(u.value, v)
|
|
elif isinstance(u, DoPrim):
|
|
for arg in u.args:
|
|
check_comb_loop_e(arg, v)
|
|
else:
|
|
...
|
|
|
|
def check_comb_loop_s(s: Statement):
|
|
if isinstance(s, Connect):
|
|
if isinstance(s.loc, (Reference, SubField, SubIndex, SubAccess)):
|
|
check_comb_loop_e(s.expr, s.loc)
|
|
elif isinstance(s, DefNode):
|
|
check_comb_loop_e(s.value, Reference(s.name, s.value.typ))
|
|
elif isinstance(s, Conditionally):
|
|
check_comb_loop_s(s.conseq)
|
|
check_comb_loop_s(s.alt)
|
|
elif isinstance(s, EmptyStmt):
|
|
...
|
|
elif isinstance(s, Block):
|
|
for stmt in s.stmts:
|
|
check_comb_loop_s(stmt)
|
|
|
|
def get_reg_map(s: Statement):
|
|
if isinstance(s, Block):
|
|
for sx in s.stmts:
|
|
if isinstance(sx, DefRegister):
|
|
CheckCombLoop.reg_map[sx.name] = sx
|
|
elif isinstance(sx, DefMemPort):
|
|
CheckCombLoop.reg_map[f"{sx.mem.name}_{sx.name}_data"] = DefWire(f"{sx.mem.name}_{sx.name}_data",
|
|
UIntType(IntWidth(sx.mem.typ.size)))
|
|
CheckCombLoop.reg_map[f"{sx.mem.name}_{sx.name}_addr"] = DefWire(f"{sx.mem.name}_{sx.name}_addr",
|
|
UIntType(IntWidth(get_binary_width(sx.mem.typ.size))))
|
|
CheckCombLoop.reg_map[f"{sx.mem.name}_{sx.name}_en"] = DefWire(f"{sx.mem.name}_{sx.name}_en",
|
|
UIntType(IntWidth(1)))
|
|
if sx.rw is False:
|
|
CheckCombLoop.reg_map[f"{sx.mem.name}_{sx.name}_mask"] = DefWire(f"{sx.mem.name}_{sx.name}_mask",
|
|
UIntType(IntWidth(1)))
|
|
else:
|
|
...
|
|
elif isinstance(s, EmptyStmt):
|
|
...
|
|
elif isinstance(s, Conditionally):
|
|
get_reg_map(s.conseq)
|
|
get_reg_map(s.alt)
|
|
|
|
get_reg_map(stmt)
|
|
check_comb_loop_s(stmt)
|
|
|
|
return stmt
|