forked from opendacs/PyHCL
59 lines
1.9 KiB
Python
59 lines
1.9 KiB
Python
import os
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from collections import Counter
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from typing import Dict
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from pyhcl.core._dynamic_ctx import DynamicContext
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from pyhcl.core._emit_context import EmitterContext
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from pyhcl.dsl.module import Module
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from pyhcl.ir import low_ir
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from pyhcl.util.firrtltools import replacewithfirmod
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from pyhcl.dsl.stage import Form, HighForm
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class Emitter:
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@staticmethod
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def elaborate(m: Module) -> low_ir.Circuit:
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ec: EmitterContext = EmitterContext(m, {}, Counter())
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modIRs: Dict[int, low_ir.DefModule] = ec.emit()
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modIRs = replacewithfirmod(modIRs)
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circuit = low_ir.Circuit(list(modIRs.values()), ec.name)
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DynamicContext.clearScope()
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return circuit
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@staticmethod
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def emit(m: Module, f: Form = HighForm) -> str:
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return f(Emitter.elaborate(m)).emit()
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@staticmethod
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def dump(s, filename) -> str:
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dir_name = "." + filename.split(".")[-1]
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if not os.path.exists(dir_name):
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os.mkdir(dir_name)
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f = os.path.join(dir_name, filename)
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with open(f, "w+") as fir_file:
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fir_file.write(s)
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return f
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@staticmethod
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def dumpVerilog(filename, use_jar=False):
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if use_jar:
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os.system('java -jar firrtl.jar -i %s -o %s -X verilog' % (filename, filename))
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else:
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os.system('firrtl -i %s -o %s -X verilog' % (filename, filename))
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@staticmethod
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def dumpMidForm(filename, use_jar=False):
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if use_jar:
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os.system('java -jar firrtl.jar -i %s -o %s -X middle' % (filename, filename))
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else:
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os.system('firrtl -i %s -o %s -X middle' % (filename, filename))
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@staticmethod
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def dumpLoweredForm(filename, use_jar):
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if use_jar:
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os.system('java -jar firrtl.jar -i %s -o %s -X low' % (filename, filename))
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else:
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os.system('firrtl -i %s -o %s -X low' % (filename, filename))
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