forked from opendacs/PyHCL
40 lines
897 B
Python
40 lines
897 B
Python
from pyhcl import *
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from pyhcl.simulator import Simlite
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class HalfAdder(Module):
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io = IO(
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a=Input(U.w(1)),
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b=Input(U.w(1)),
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s=Output(U.w(1)),
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cout=Output(U.w(1))
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)
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# 填充完整输出端口s以及cout的逻辑，例如：
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io.s @= io.a ^ io.b
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io.cout @= io.a & io.b
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def main():
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Emitter.dumpVerilog(Emitter.dump(Emitter.emit(HalfAdder()), "HalfAdder.fir"))
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# cfg = DpiConfig()
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s = Simlite(HalfAdder())
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# s.start()
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# s.step([20, 20])
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# s.step([15, 10])
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# s.step([1000, 1])
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# s.step([999, 201])
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# s.close()
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# 生成Verilog文件
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if __name__ == '__main__':
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Emitter.dumpVerilog(Emitter.dump(Emitter.emit(HalfAdder()), "HalfAdder.fir"))
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# cfg = DpiConfig()
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s = Simlite(HalfAdder())
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s.start()
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s.step([20, 20])
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s.step([15, 10])
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s.step([1000, 1])
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s.step([999, 201])
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s.close()
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