forked from opendacs/PyHCL
78 lines
2.2 KiB
Python
78 lines
2.2 KiB
Python
from pyhcl import *
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class Inst:
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ADD = BitPat("0000000??????????000?????0110011")
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SUB = BitPat("0100000??????????000?????0110011")
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AND = BitPat("0000000??????????111?????0110011")
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OR = BitPat("0000000??????????110?????0110011")
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LW = BitPat("?????????????????010?????0000011")
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SW = BitPat("?????????????????010?????0100011")
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class Control:
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# ALUOP
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ALUOP_XXX = U(0)
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ALUOP_ADD = U(0)
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ALUOP_SUB = U(1)
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ALUOP_AND = U(2)
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ALUOP_OR = U(3)
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# MEM_READ
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MEM_READ_FALSE = U(0)
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MEM_READ_TRUE = U(1)
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# MEM_WRITE
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MEM_WRITE_FALSE = U(0)
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MEM_WRITE_TRUE = U(1)
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# REG_WRITE
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REG_WRITE_FALSE = U(0)
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REG_WRITE_TRUE = U(1)
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# map dict
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map = {
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Inst.ADD: VecInit([ALUOP_ADD, MEM_READ_FALSE, MEM_WRITE_FALSE, REG_WRITE_TRUE]),
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Inst.SUB: VecInit([ALUOP_SUB, MEM_READ_FALSE, MEM_WRITE_FALSE, REG_WRITE_TRUE]),
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Inst.AND: VecInit([ALUOP_AND, MEM_READ_FALSE, MEM_WRITE_FALSE, REG_WRITE_TRUE]),
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Inst.OR: VecInit([ALUOP_OR, MEM_READ_FALSE, MEM_WRITE_FALSE, REG_WRITE_TRUE]),
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Inst.LW: VecInit([ALUOP_XXX, MEM_READ_TRUE, MEM_WRITE_FALSE, REG_WRITE_TRUE]),
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Inst.SW: VecInit([ALUOP_XXX, MEM_READ_FALSE, MEM_WRITE_TRUE, REG_WRITE_FALSE]),
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...: VecInit([ALUOP_XXX, MEM_READ_FALSE, MEM_WRITE_FALSE, REG_WRITE_FALSE])
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}
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class BitPadTest(Module):
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io = IO(
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inst=Input(U.w(32)),
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ALUOP=Output(U.w(32)),
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MEM_READ=Output(U.w(32)),
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MEM_WRITE=Output(U.w(32)),
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REG_WRITE=Output(U.w(32)),
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a=Input(U.w(32)),
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b=Input(U.w(32)),
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v=Input(Vec(4, U.w(32))),
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out=Output(U.w(32)),
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)
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stmt_list = LookUpTable(io.inst, {
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Inst.ADD: VecInit([io.a * io.b, io.a / io.b, io.a ^ io.b, io.a % io.b]),
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Inst.SUB: VecInit([io.a == io.b, io.a != io.b, io.a < io.b, io.a > io.b]),
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...: VecInit([io.a + io.b, io.a - io.b, io.a & io.b, io.a | io.b])
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})
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sum = Sum(io.v)
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io.out @= Sum(stmt_list) + sum
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ctrl_signal = LookUpTable(io.inst, Control.map)
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v = VecInit([io.ALUOP, io.MEM_READ, io.MEM_WRITE, io.REG_WRITE])
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v @= ctrl_signal
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if __name__ == '__main__':
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f = Emitter.dump(Emitter.emit(BitPadTest()), "bitpat.dir")
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Emitter.dumpVerilog(f)
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