forked from opendacs/PyHCL
50 lines
1.6 KiB
Python
50 lines
1.6 KiB
Python
# https://gitlink
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from pyhcl import *
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class Addr_Buffer(Module):
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io = IO(
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addr_input=Input(U.w(32)),
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flush=Input(Bool),
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record=Input(Bool),
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front=Output(U.w(32)),
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)
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buffer = Mem(3, U.w(32))
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counter = Mem(3, U.w(2))
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is_used = Mem(3, Bool)
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io.front @= Mux(counter[U(0)] > counter[U(1)],
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Mux(counter[U(0)] > counter[U(2)], buffer[U(0)], buffer[U(2)]),
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Mux(counter[U(1)] > counter[U(2)], buffer[U(1)], buffer[U(2)]))
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write_index = Mux(is_used[U(0)] == U(0), U(0), Mux(is_used[U(1)] == U(0), U(1), U(2)))
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temp_used_list = []
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for i in range(0, 3):
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temp_used_list.append(Mux(io.record.to_bool(), Mux(write_index == U(i), Bool(1), is_used[U(i)]),
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is_used[U(i)]))
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for i in range(0, 3):
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is_used[U(i)] @= Mux(io.flush.to_bool(), Bool(0), Mux(counter[U(i)] == U(2), Bool(0), temp_used_list[i]))
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for i in range(0, 3):
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counter[U(i)] @= Mux(io.flush.to_bool(), U(0),
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Mux(counter[U(i)] == U(2), U(0),
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Mux(is_used[U(i)], counter[U(i)] + U(1), counter[U(i)])))
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for i in range(0, 3):
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buffer[U(i)] @= Mux(io.flush.to_bool(), U(0),
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Mux(counter[U(i)] == U(2), U(0),
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Mux(io.record.to_bool(),
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Mux(write_index == U(i), io.addr_input, buffer[U(i)]), buffer[U(i)])))
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def main():
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Emitter.dumpVerilog(Emitter.dump(Emitter.emit(Addr_Buffer()), "adder_buf.dir"))
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if __name__ == '__main__':
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main()
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