forked from opendacs/PyHCL
128 lines
1.7 KiB
Markdown
128 lines
1.7 KiB
Markdown
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# Assignment overlap
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## Introduction
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Pyhcl will check that no signal assignment completely erases a previous one.
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## Example
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The following code
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```scala
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class TopLevel extends Component {
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val a = UInt(8 bits)
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a := 42
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a := 66 // Erase the a := 42 assignment
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}
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```
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will throw the following error:
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```
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ASSIGNMENT OVERLAP completely the previous one of (toplevel/a : UInt[8 bits])
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***
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Source file location of the a := 66 assignment via the stack trace
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***
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```
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A fix could be:
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```python
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class TopLevel extends Component {
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val a = UInt(8 bits)
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a := 42
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when(something) {
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a := 66
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}
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}
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```
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But in the case when you really want to override the previous assignment (as there are times when overriding makes sense), you can do the following:
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```scala
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class TopLevel extends Component {
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val a = UInt(8 bits)
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a := 42
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a.allowOverride
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a := 66
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}
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```
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# Clock Crossing violation
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## Introduction
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## example
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### crossClockDomain tag
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### setSyncronouswith
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### BufferCC
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# Combinatorial loop
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## Introduction
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## example
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## False-positives
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# Hierarchy violation
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## Introduction
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## example
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# IO Bundel
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## Introduction
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## example
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# Latch detected
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## Introduction
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## example
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# No driver on
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## Introduction
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## example
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# NullPointerException
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## Introduction
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## example
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### Issue explanation
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# Register defined as component input
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## Introduction
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## example
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# Scope violation
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## Introduction
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## example
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# PyHCL can't clone class
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## Introduction
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## Example1
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## Example2
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# Unassigned register
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## Introduction
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## Example
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## Register with only init
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# Unreachable is statement
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## Introduction
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## Example
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# Width mismatch
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## Assignment example
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## Operator example
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# Introduction |