add copyright & license

Co-authored-by: laixz <laixz@scut.edu.cn>
Co-committed-by: laixz <laixz@scut.edu.cn>

example/ALU.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from pyhcl.simulator import Simulator
 

example/Adder.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from pyhcl.simulator import Simulator
 

example/Adder_Buf.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 

example/Assert.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 

example/Bitpat.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 

example/Blackbox.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 

example/ClockDomin.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 class A(Module):

example/Filter.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from functools import reduce
 from typing import List
 

example/Firrtl.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 class Add(BlackBox):

example/Full_Adder.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 

example/GCD.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 

example/MatrixMul.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 

example/MaxN.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from functools import reduce
 
 from pyhcl import *

example/Mem.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 

example/Mul.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 

example/Neurons.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 W = 8  # 位宽

example/Qemu.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from pprint import pprint
 from time import time

example/ShiftRegister.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 

example/Simlite_task.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from pysv import sv, DataType, Reference
 from pyhcl.simulator import Simlite, DpiConfig

example/half_adder.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from pyhcl.simulator import Simlite
 

example/muxVec.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 

example/pysvusage.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 import random
 
 from pyhcl import *

example/simlite.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from pysv import sv, DataType, Reference
 from pyhcl.simulator import Simlite, DpiConfig

example/simlite_2.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from pysv import sv, DataType, Reference
 from pyhcl.simulator import Simlite, DpiConfig

example/test.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from functools import reduce
 
 from pyhcl import *

injector/reader.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 
 # 读波形
 from injector.vcd_reader import VcdReader

injector/reader_base.py

@@ -1,3 +1,7 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
+
 class ReaderBase:
     # 属性：excluded_sigs、inputs_only、replay_blocks、signal_values、signal_changes
     def __init__(self, replay_blocks, wave_file, excluded_sigs, inputs_only):     

injector/simlite_v1.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from pysv import sv, DataType, Reference
 from pyhcl.simulator import Simlite, DpiConfig

injector/simlite_v2.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from pysv import sv, DataType, Reference
 from pyhcl.simulator import Simlite, DpiConfig

injector/simlite_v3.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from pysv import sv, DataType, Reference
 from pyhcl.simulator import Simlite, DpiConfig

injector/simlite_v4.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 # from pyhcl import *
 # from pysv import sv, DataType, Reference
 # from pyhcl.simulator import Simlite, DpiConfig

injector/vcd_reader.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 import os
 import sys
 import re

main.py

@@ -1,3 +1,7 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
+
 from pyhcl import *
 
 class FullAdder(Module):

myTests/test.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from typing import Type, Union, Dict
 
 

myTests/test_async.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 # Eventloop 是asyncio应用的核心,把一些异步函数注册到这个事件循环上，事件循环会循环执行这些函数,
 # 当执行到某个函数时，如果它正在等待I/O返回，如它正在进行网络请求，或者sleep操作，事件循环会暂停它的执行去执行其他的函数；
 # 当某个函数完成I/O后会恢复，下次循环到它的时候继续执行。

myTests/test_async_2.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 import asyncio
 import time
 

myTests/test_firrtl.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from pyhcl.util.firrtltools import addfirrtlmodule
 from pyhcl.simulator import Simlite

myTests/test_firrtl_2.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl.simulator.simlite_firrtl import Simlite
 import random
 

myTests/test_simlite.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from pyhcl.simulator import Simlite
 import random

myTests/test_simlite_fork.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from pyhcl.simulator import Simlite
 import random

myTests/test_simlite_pysv.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from pysv import sv, DataType, Reference
 from pyhcl.simulator import Simlite, DpiConfig

myTests/test_verilog.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl.simulator.simlite_verilog import Simlite
 import random
 

myTests/test_verilog_fork.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl.simulator.simlite_verilog import Simlite
 import random
 

myTests/test_verilog_pysv.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl.util.pysvtools import compile_and_binding_all_func
 from pyhcl.simulator.simlite_verilog import Simlite, DpiConfig
 from pysv import sv, DataType, Reference

pyhcl/core/_clock_manager.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 class Clock_manager:
     _clocks = []
     _resets = []

pyhcl/core/_cond.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from __future__ import annotations
 from dataclasses import dataclass, field
 from typing import List

pyhcl/core/_dynamic_ctx.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 class DynamicContext:
     _lst = []
     _scopeId = [object()]

pyhcl/core/_emit_context.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from collections import deque
 from typing import Optional, Dict, Counter
 

pyhcl/core/_interface.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl.core._utils import get_attr
 
 

pyhcl/core/_meta_pub.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl.core._repr import Node
 from pyhcl.core._utils import get_attr, has_attr
 

pyhcl/core/_repr.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 import logging
 from dataclasses import dataclass, field
 from typing import Union

pyhcl/core/_utils.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 def get_attr(obj, item):
     try:
         return object.__getattribute__(obj, item)

pyhcl/dsl/bundle.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from __future__ import annotations
 
 from dataclasses import dataclass

pyhcl/dsl/cdatatype.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from dataclasses import dataclass
 from typing import Optional
 

pyhcl/dsl/cio.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from __future__ import annotations
 
 from dataclasses import dataclass

pyhcl/dsl/clockdomin.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl.core._clock_manager import Clock_manager
 
 class clockdomin:

pyhcl/dsl/condition.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from __future__ import annotations
 
 from pyhcl.core._cond import CondBlock, When, Elsewhen, Otherwise

pyhcl/dsl/dslchecker.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl.core._clock_manager import Clock_manager
 
 class DslChecker:

pyhcl/dsl/emitter.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 import os
 from collections import Counter
 from typing import Dict

pyhcl/dsl/funcs.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from functools import reduce
 
 

pyhcl/dsl/infra.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from dataclasses import dataclass, field
 from typing import Type, Union
 

pyhcl/dsl/memory.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from __future__ import annotations
 from dataclasses import dataclass, field, InitVar
 

pyhcl/dsl/module.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl.core._dynamic_ctx import DynamicContext
 from pyhcl.core._utils import get_attr
 from pyhcl.core._repr import SubField

pyhcl/dsl/module_p.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from .module import Module
 
 class ModuleP:

pyhcl/dsl/stage.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from abc import ABC, abstractclassmethod
 from dataclasses import dataclass
 

pyhcl/dsl/vector.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from dataclasses import dataclass, field
 from typing import Union, Generator, List
 

pyhcl/dsl/verifaction.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl.ir import low_ir
 from pyhcl.core._dynamic_ctx import DynamicContext
 

pyhcl/ir/low_ir.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from __future__ import annotations
 
 from abc import ABC

pyhcl/ir/low_node.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from abc import ABC, abstractmethod
 
 

pyhcl/ir/low_prim.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 import logging
 from abc import ABC
 from dataclasses import dataclass

pyhcl/ir/utils.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 import math
 from collections import OrderedDict, defaultdict
 from copy import copy, deepcopy

pyhcl/lib/axi/axi.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from .channel import AxiIOFactory
 

pyhcl/lib/axi/channel.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 
 """

pyhcl/lib/fifo/fifo.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl import *
 from enum import Enum
 

pyhcl/passes/_pass.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from typing import List
 
 class Pass:

pyhcl/passes/auto_inferring.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from dataclasses import dataclass
 from typing import Dict, List
 from pyhcl.ir.low_ir import *

pyhcl/passes/check_flows.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from typing import List
 from pyhcl.ir.low_ir import *
 from pyhcl.ir.low_prim import *

pyhcl/passes/check_form.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from typing import List
 from pyhcl.ir.low_ir import *
 from pyhcl.ir.low_prim import *

pyhcl/passes/check_types.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from typing import List
 
 from pyhcl.ir.low_ir import *

pyhcl/passes/check_widths.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from typing import List
 from pyhcl.ir.low_ir import *
 from pyhcl.ir.low_prim import *

pyhcl/passes/expand_aggregate.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from typing import List
 from pyhcl.ir.low_ir import *
 from pyhcl.ir.low_prim import *

pyhcl/passes/expand_memory.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from typing import List, Dict
 from pyhcl.ir.low_ir import *
 from pyhcl.ir.low_prim import *

pyhcl/passes/expand_sequential.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl.ir.low_ir import *
 from pyhcl.ir.low_prim import *
 from typing import List, Dict

pyhcl/passes/expand_whens.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from typing import List
 
 from numpy import isin

pyhcl/passes/handle_instance.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from dataclasses import dataclass
 from typing import List, Dict
 from pyhcl.ir.low_ir import *

pyhcl/passes/optimize.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from typing import List, Dict
 from pyhcl.ir.low_ir import *
 from pyhcl.ir.low_prim import *

pyhcl/passes/remove_access.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from pyhcl.ir.low_ir import *
 from typing import List
 from dataclasses import dataclass

pyhcl/passes/replace_subaccess.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from sqlite3 import connect
 from typing import List
 from pyhcl.ir.low_ir import *

pyhcl/passes/utils.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 import math
 
 from typing import List

pyhcl/passes/verilog_optimize.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from dataclasses import dataclass
 from pyhcl.ir.low_ir import *
 from pyhcl.passes._pass import Pass

pyhcl/passes/wir.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from abc import ABC
 from pyhcl.ir.low_ir import *
 

pyhcl/simulator/sim.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 import logging
 import mmap
 import os

pyhcl/simulator/simlite.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 import os
 import subprocess
 

pyhcl/simulator/simlite_firrtl.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 import os
 import subprocess
 

pyhcl/simulator/simlite_verilog.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 import os
 import subprocess
 import re

pyhcl/simulator/src/simulator.h

@@ -1,3 +1,6 @@
+// Copyright (c) 2019 scutdig
+// Licensed under the MIT license.
+
 #include <verilated.h>
 #include <verilated_vcd_c.h>
 #include <iostream>

pyhcl/tester/clock_stepper.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from abc import ABC, abstractclassmethod
 from typing import List
 from pyhcl.ir.low_ir import *

pyhcl/tester/compiler.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from functools import reduce
 from pyhcl.ir.low_ir import *
 from pyhcl.ir.low_prim import *

pyhcl/tester/exception.py

@@ -1,3 +1,7 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
+
 class TesterException(Exception):
     def __init__(self, message: str):
         self.message = message

pyhcl/tester/executer.py

@@ -1,3 +1,6 @@
+# Copyright (c) 2019 scutdig
+# Licensed under the MIT license.
+
 from typing import Dict, List
 from collections import OrderedDict
 from copy import deepcopy