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PyHCL
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183 Commits

Author SHA1 Message Date
wissy d59af5abab fix add 2023-01-08 11:55:17 +08:00
GH Cheng 2042012736 fix docs 2022-07-25 16:18:01 +08:00
GH Cheng dd69d2bd9c fix docs 2022-07-25 16:18:01 +08:00
GH Cheng 536545c43a fix docs & <<= -> @= 2022-07-25 16:18:01 +08:00
Guanghui Cheng c482041e44
Merge pull request #58 from Mosk0ng/master 
fix & add docs
 2022-07-16 14:19:14 +08:00
Mosk0ng 6c20d181b8
Merge pull request #4 from raybdzhou/master 
new features
 2022-07-16 14:05:30 +08:00
Mosk0ng aa99bf9377
Merge branch 'master' into master 2022-07-16 14:04:45 +08:00
Mosk0ng 26446417b9
Merge pull request #3 from wissygh/master 
docs fix
 2022-07-16 14:02:43 +08:00
Guanghui Cheng 8dca171707
Delete .travis.yml 2022-07-16 13:58:11 +08:00
Guanghui Cheng 73518479d4
Update .travis.yml 2022-07-16 13:54:15 +08:00
Guanghui Cheng 85a8f4f710
Update .travis.yml 2022-07-16 13:50:36 +08:00
Guanghui Cheng 4720816cc0
Merge branch 'Mosk0ng:master' into master 2022-07-15 19:07:15 +08:00
raybdzhou 5bd670056a fix: errors in sequential logic simulation 2022-06-27 14:45:53 +08:00
raybdzhou f9ee7ef39f fix: bugs in expand_whens 2022-06-25 16:04:07 +08:00
raybdzhou 5737c475d6 feat: simulation on low form 2022-06-21 10:45:11 +08:00
raybdzhou ae07f5991a refactor: remove instance manager 2022-06-20 09:31:38 +08:00
raybdzhou 76b6d81049 refactor: remove dsl/check_and_infer 2022-06-13 20:23:33 +08:00
raybdzhou ca652407fa refactor: func verilog_serialize in low_ir 2022-06-11 19:17:56 +08:00
raybdzhou 6e67aa3675 fix: bugs in replace_subaccess 2022-06-10 22:00:07 +08:00
raybdzhou c94f326cd7 refactor: remove infer_types & infer_widths 2022-06-10 21:03:12 +08:00
raybdzhou db3333abda refactor: remove replace_subindex 2022-06-10 19:33:59 +08:00
raybdzhou 8b1b849df5 feat: add verilog_optimize 2022-06-10 17:49:38 +08:00
raybdzhou 123ee6d643 fix: some bugs in replace_subaccess 2022-06-10 17:14:00 +08:00
raybdzhou 2e34e0a979 feat: add SingleClockStepper 2022-05-28 09:03:57 +08:00
raybdzhou 9858c6b4dd Merge remote-tracking branch 'upstream/master' 2022-05-15 18:30:28 +08:00
raybdzhou d5dfe325d9 feat: add execution scheduler 2022-05-15 18:14:49 +08:00
raybdzhou 08edc6ad4d feat: compiler of tester on high firrtl 2022-05-10 18:22:58 +08:00
Mosk0ng 7bd1f7600b
Merge pull request #2 from lx071/master 
verilog_simlite
 2022-05-09 12:53:41 +08:00
lx071 514b6e1ab3 Merge branch 'Mosk0ng-master' 2022-05-09 12:33:52 +08:00
lx071 a1d43175aa update 2022-05-09 12:33:26 +08:00
lx071 43bfe39733 update 2022-05-09 12:26:34 +08:00
lx071 7668238035 update 2022-05-09 12:17:10 +08:00
lx071 1630baacb2 update 2022-05-09 10:23:10 +08:00
lx071 ea1318e009 Merge branch 'master' of github.com:lx071/PyChip-py-hcl 2022-05-08 20:17:11 +08:00
lx071 61d50c6c78 update 2022-05-08 20:14:50 +08:00
Msk 92310f9a74 Add example of firrtltool 2022-05-08 18:04:34 +08:00
lx071 9fec412541
Merge branch 'Mosk0ng:master' into master 2022-05-08 12:40:05 +08:00
lx071 cf0da745fe update 2022-05-08 10:55:20 +08:00
lx071 2e6460a5b8 update 2022-05-07 22:16:40 +08:00
lx071 833cda7f60 update 2022-05-07 21:56:42 +08:00
lx071 8ffb03b807 update 2022-05-07 19:46:09 +08:00
lx071 f0920bf953 update 2022-05-07 17:47:55 +08:00
lx071 820aa3ab0b update 2022-05-07 17:19:27 +08:00
lx071 0fd231483e update 2022-05-07 17:00:34 +08:00
lx071 a00a0c7e39 update 2022-05-07 16:59:32 +08:00
lx071 bd359a36ae update 2022-05-07 12:35:02 +08:00
lx071 dce48428d9 update 2022-05-06 23:21:52 +08:00
lx071 a21905fadb update 2022-05-06 21:09:14 +08:00
GH Cheng 42c72eefac docs fix 2022-05-06 10:57:20 +08:00
raybdzhou 0fd2671afc fix: ExpandSubAccess in emitting lowered FIRRTL 2022-05-06 10:30:25 +08:00