forked from opendacs/PyHCL
refactor: remove infer_types & infer_widths
This commit is contained in:
raybdzhou
parent
db3333abda
commit
c94f326cd7
4
main.py
4
main.py
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@ -17,8 +17,8 @@ class FullAdder(Module):
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if __name__ == '__main__':
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# emit high firrtl
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# Emitter.dump(Emitter.emit(FullAdder(), HighForm), "FullAdder.fir")
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Emitter.dump(Emitter.emit(FullAdder(), HighForm), "FullAdder.fir")
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# emit lowered firrtl
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# Emitter.dump(Emitter.emit(FullAdder(), LowForm), "FullAdder.lo.fir")
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Emitter.dump(Emitter.emit(FullAdder(), LowForm), "FullAdder.lo.fir")
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# emit verilog
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Emitter.dump(Emitter.emit(FullAdder(), Verilog), "FullAdder.v")
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@ -1,11 +1,10 @@
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from pyhcl.passes import check_form, check_types, check_widths, check_flows, infer_types, infer_widths
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from pyhcl.passes import check_form, check_types, check_widths, check_flows, auto_inferring
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from pyhcl.ir.low_ir import *
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class CheckAndInfer:
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@staticmethod
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def run(c: Circuit):
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c = check_form.CheckHighForm(c).run()
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c = infer_types.InferTypes().run(c)
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c = infer_widths.InferWidths().run(c)
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c = auto_inferring.AutoInferring().run(c)
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c = check_types.CheckTypes().run(c)
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c = check_flows.CheckFlow().run(c)
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c = check_widths.CheckWidths().run(c)
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@ -0,0 +1,124 @@
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from dataclasses import dataclass
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from typing import Dict, List
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from pyhcl.ir.low_ir import *
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@dataclass
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class AutoInferring:
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max_width: int = 0
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def run(self, c: Circuit):
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modules: List[Module] = []
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def auto_inferring_t(t: Type) -> Type:
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if isinstance(t, UIntType):
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if t.width.width == 0:
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return UIntType(IntWidth(self.max_width))
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else:
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self.max_width = self.max_width if self.max_width > t.width.width else t.width.width
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return t
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elif isinstance(t, SIntType):
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if t.width.width == 0:
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return SIntType(IntWidth(self.max_width))
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else:
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self.max_width = self.max_width if self.max_width > t.width.width else t.width.width
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return t
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elif isinstance(t, (ClockType, ResetType, AsyncResetType)):
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return t
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elif isinstance(t, VectorType):
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return VectorType(auto_inferring_t(t.typ), t.size)
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elif isinstance(t, MemoryType):
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return MemoryType(auto_inferring_t(t.typ), t.size)
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elif isinstance(t, BundleType):
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return BundleType([Field(fx.name, fx.flip, auto_inferring_t(fx.typ)) for fx in t.fields])
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else:
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return t
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def auto_inferring_e(e: Expression, inferring_map: Dict[str, Type]) -> Expression:
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if isinstance(e, Mux):
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return Mux(auto_inferring_e(e.cond, inferring_map), auto_inferring_e(e.tval, inferring_map),
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auto_inferring_e(e.fval, inferring_map), auto_inferring_t(e.typ))
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elif isinstance(e, ValidIf):
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return ValidIf(auto_inferring_e(e.cond, inferring_map), auto_inferring_e(e.value, inferring_map), auto_inferring_t(e.typ))
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elif isinstance(e, DoPrim):
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return DoPrim(e.op, [auto_inferring_e(arg, inferring_map) for arg in e.args], e.consts, auto_inferring_t(e.typ))
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elif isinstance(e, UIntLiteral):
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if e.width.width < get_binary_width(e.value):
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return UIntLiteral(e.value, IntWidth(get_binary_width(e.value)))
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else:
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return e
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elif isinstance(e, SIntLiteral):
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if e.width.width < get_binary_width(e.value) + 1:
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return SIntLiteral(e.value, IntWidth(get_binary_width(e.value)))
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else:
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return e
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elif isinstance(e, Reference):
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typ = inferring_map[e.name] if inferring_map[e.name] else auto_inferring_t(e.typ)
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return Reference(e.name, typ)
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elif isinstance(e, SubField):
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expr = auto_inferring_e(e.expr, inferring_map)
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typ = e.typ
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for fx in expr.typ.fields:
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if fx.name == e.name:
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typ = fx.typ
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return SubField(expr, e.name, typ)
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elif isinstance(e, SubIndex):
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expr = auto_inferring_e(e.expr, inferring_map)
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return SubIndex(e.name, expr, e.value, expr.typ.typ)
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elif isinstance(e, SubAccess):
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expr = auto_inferring_e(e.expr, inferring_map)
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index = auto_inferring_e(e.index, inferring_map)
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return SubAccess(expr, index, expr.typ.typ)
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else:
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return e
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def auto_inferring_s(s: Statement, inferring_map: Dict[str, Type]) -> Statement:
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if isinstance(s, Block):
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stmts: List[Statement] = []
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for sx in s.stmts:
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stmts.append(auto_inferring_s(sx, inferring_map))
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return Block(stmts)
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elif isinstance(s, Conditionally):
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return Conditionally(auto_inferring_e(s.pred, inferring_map), auto_inferring_s(s.conseq, inferring_map), auto_inferring_s(s.alt, inferring_map), s.info)
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elif isinstance(s, DefRegister):
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clock = auto_inferring_e(s.clock, inferring_map)
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reset = auto_inferring_e(s.reset, inferring_map)
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init = auto_inferring_e(s.init, inferring_map)
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typ = auto_inferring_t(s.typ)
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inferring_map[s.name] = typ
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return DefRegister(s.name, typ, clock, reset, init, s.info)
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elif isinstance(s, DefWire):
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inferring_map[s.name] = auto_inferring_t(s.typ)
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return s
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elif isinstance(s, DefMemory):
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inferring_map[s.name] = auto_inferring_t(s.memType)
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return s
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elif isinstance(s, DefNode):
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value = auto_inferring_e(s.value, inferring_map)
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inferring_map[s.name] = value.typ
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return DefNode(s.name, value, s.info)
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elif isinstance(s, DefMemPort):
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clk = auto_inferring_e(s.clk, inferring_map)
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index = auto_inferring_e(s.index, inferring_map)
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return DefMemPort(s.name, s.mem, index, clk, s.rw, s.info)
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elif isinstance(s, Connect):
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return Connect(auto_inferring_e(s.loc, inferring_map), auto_inferring_e(s.expr, inferring_map), s.info, s.blocking, s.bidirection, s.mem)
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else:
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return s
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def auto_inferring_m(m: DefModule, inferring_map: Dict[str, Type]) -> DefModule:
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if isinstance(m, Module):
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ports: List[Port] = []
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for p in m.ports:
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inferring_map[p.name] = auto_inferring_t(p.typ)
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ports.append(Port(p.name, p.direction, inferring_map[p.name], p.info))
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body = auto_inferring_s(m.body, inferring_map)
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return Module(m.name, ports, body, m.typ, m.info)
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else:
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return m
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for m in c.modules:
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inferring_map: Dict[str, Type] = {}
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modules.append(auto_inferring_m(m, inferring_map))
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return Circuit(modules, c.main, c.info)
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@ -1,76 +0,0 @@
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from typing import List
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from pyhcl.ir.low_ir import *
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from pyhcl.ir.low_prim import *
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from pyhcl.passes._pass import Pass
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from pyhcl.passes.wir import *
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from pyhcl.passes.utils import module_type, field_type, sub_type, mux_type, get_or_else
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class InferTypes(Pass):
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def run(self, c: Circuit) -> Circuit:
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mtyps: Dict[str, Type] = {}
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for m in c.modules:
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mtyps[m.name] = module_type(m)
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def infer_types_e(typs: Dict[str, Type], e: Expression) -> Expression:
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if isinstance(e, Reference):
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return Reference(e.name, get_or_else(e.name in typs.keys(), typs[e.name], UnknownType))
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elif isinstance(e, SubField):
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return SubField(e.expr, e.name, field_type(e.expr.typ, e.name))
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elif isinstance(e, SubIndex):
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return SubIndex(e.name, e.expr, e.value, sub_type(e.expr.typ))
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elif isinstance(e, SubAccess):
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return SubAccess(e.expr, e.index, sub_type(e.expr.typ))
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elif isinstance(e, DoPrim):
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return DoPrim(e.op, e.args, e.consts, e.typ)
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elif isinstance(e, Mux):
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return Mux(e.cond, e.tval, e.fval, mux_type(e.tval, e.fval))
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elif isinstance(e, ValidIf):
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return ValidIf(e.cond, e.value, e.value.typ)
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else:
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return e
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def infer_types_s(typs: Dict[str, Type], s: Statement) -> Statement:
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if isinstance(s, DefRegister):
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typs[s.name] = s.typ
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clock = infer_types_e(typs, s.clock) if hasattr(s, 'clock') and isinstance(s.clock, Expression) else None
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reset = s.reset if hasattr(s, 'reset') and isinstance(s.init, Expression) else Reference('reset', ResetType())
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init = s.init if hasattr(s, 'init') and isinstance(s.init, Expression) else Reference(s.name, s.typ)
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return DefRegister(s.name, s.typ, clock, reset, init, s.info)
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elif isinstance(s, DefWire):
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typs[s.name] = s.typ
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return s
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elif isinstance(s, DefNode):
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value = infer_types_e(typs, s.value) if hasattr(s, 'value') and isinstance(s.value, Expression) else None
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typs[s.name] = s.value.typ
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return DefNode(s.name, value, s.info)
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elif isinstance(s, DefMemory):
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typs[s.name] = s.memType
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return s
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elif isinstance(s, DefInstance):
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typs[s.name] = mtyps[s.module]
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return s
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else:
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return s
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def infer_types_p(typs: set, p: Port) -> Port:
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typs[p.name] = p.typ
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return p
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def infer_types(m: DefModule) -> DefModule:
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if isinstance(m, ExtModule):
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return m
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types: Dict[str, Type] = {}
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ports = None
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stmts = None
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if hasattr(m, 'ports') and isinstance(m.ports, list):
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ports = list(map(lambda p: infer_types_p(types, p), m.ports))
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if hasattr(m, 'body') and isinstance(m.body, Block):
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if hasattr(m.body, 'stmts') and isinstance(m.body.stmts, list):
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stmts = list(map(lambda s: infer_types_s(types, s), m.body.stmts))
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return Module(m.name, ports, Block(stmts), m.typ, m.info)
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res = list(map(lambda m: infer_types(m), c.modules))
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return Circuit(res, c.main, c.info)
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@ -1,100 +0,0 @@
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from typing import List
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from pyhcl.ir.low_ir import *
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from pyhcl.ir.low_prim import *
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from pyhcl.passes._pass import Pass
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from pyhcl.passes.wir import *
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class InferWidths(Pass):
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@staticmethod
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def run(c: Circuit):
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def infer_widths_t(widths: Dict[str, Width], name: str, t: Type):
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if isinstance(t, BundleType):
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bs = list(map(lambda f: infer_widths_t(widths, name, f.typ), t.fields))
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bs = [b for b in bs if b is not None].pop()
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t, widths = bs[0], bs[1]
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elif isinstance(t, MemoryType):
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return infer_widths_t(widths, name, t.typ)
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elif isinstance(t, VectorType):
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return infer_widths_t(widths, name, t.typ)
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elif isinstance(t, UIntType):
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if isinstance(t.width, UnknownWidth):
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return UIntType(widths.values().pop()), widths.clear()
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else:
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widths[name] = t.width
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elif isinstance(t, SIntType):
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if isinstance(t.width, UnknownWidth):
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return SIntType(widths.values().pop()), widths.clear()
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else:
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widths[name] = t.width
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elif isinstance(t, ClockType):
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if isinstance(t.width, UnknownWidth):
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return ClockType(widths.values().pop()), widths.clear()
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else:
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widths[name] = t.width
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elif isinstance(t, ResetType):
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if isinstance(t.width, UnknownWidth):
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return ResetType(widths.values().pop()), widths.clear()
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else:
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widths[name] = t.width
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elif isinstance(t, AsyncResetType):
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if isinstance(t.width, UnknownWidth):
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return AsyncResetType(widths.values().pop()), widths.clear()
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else:
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widths[name] = t.width
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return t, widths
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def infer_widths_e(widths: Dict[str, Width], e: Expression):
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if isinstance(e, UIntLiteral):
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return e, widths
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elif isinstance(e, SIntLiteral):
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return e, widths
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elif isinstance(e, SubField):
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t, widths = infer_widths_t(widths, e.name, e.typ)
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return SubField(e.expr, e.name, t), widths
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elif isinstance(e, SubAccess):
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t, widths = infer_widths_t(widths, '', e.typ)
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return SubAccess(e.expr, e.index, t), widths
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elif isinstance(e, SubIndex):
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t, widths = infer_widths_t(widths, e.name, e.typ)
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return SubIndex(e.name, e.expr, e.value, t), widths
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elif isinstance(e, DoPrim):
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t, widths = infer_widths_t(widths, '', e.typ)
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return DoPrim(e.op, e.args, e.consts, t), widths
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elif isinstance(e, Mux):
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t, widths = infer_widths_t(widths, '', e.typ)
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return Mux(e.cond, e.tval, e.fval, t), widths
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elif isinstance(e, ValidIf):
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t, widths = infer_widths_t(widths, '', e.typ)
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return Mux(e.cond, e.value, t), widths
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else:
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t, widths = infer_widths_t(widths, e.name, e.typ)
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return Reference(e.name, t), widths
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def infer_widths_s(widths: Dict[str, Width], s: Statement):
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if isinstance(s, Connect):
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expr, widths = infer_widths_e(widths, s.expr)
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loc, widths = infer_widths_e(widths, s.loc)
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return Connect(loc, expr, s.info)
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return s
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def infer_widths_m(m: DefModule) -> DefModule:
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if isinstance(m, ExtModule):
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return m
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widths: Dict[str, Width] = {}
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stmts = None
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if hasattr(m, 'body') and isinstance(m.body, Block):
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if hasattr(m.body, 'stmts') and isinstance(m.body.stmts, list):
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stmts = list(map(lambda s: infer_widths_s(widths, s), m.body.stmts))
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return Module(m.name, m.ports, Block(stmts), m.typ, m.info)
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return Circuit(list(map(lambda m: infer_widths_m(m), c.modules)), c.main, c.info)
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