forked from opendacs/PyHCL
firrtl_ir: add uint/sint test
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# Py-HCL
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[![Build Status](https://travis-ci.com/scutdig/pyHCL.svg?branch=master)](https://travis-ci.com/scutdig/pyHCL)
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[![Build Status](https://travis-ci.com/scutdig/py-hcl.svg?branch=master)](https://travis-ci.com/scutdig/py-hcl)
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[![codecov](https://codecov.io/gh/scutdig/py-hcl/branch/master/graph/badge.svg)](https://codecov.io/gh/scutdig/py-hcl)
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A Hardware Construct Language
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@ -10,6 +10,18 @@ def test_clock_type():
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serialize_equal(tpe.ClockType(), "Clock")
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def test_uint_type():
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serialize_equal(tpe.UIntType(width.UnknownWidth()), "UInt")
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serialize_equal(tpe.UIntType(width.IntWidth(8)), "UInt<8>")
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serialize_equal(tpe.UIntType(width.IntWidth(32)), "UInt<32>")
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def test_sint_type():
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serialize_equal(tpe.SIntType(width.UnknownWidth()), "SInt")
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serialize_equal(tpe.SIntType(width.IntWidth(8)), "SInt<8>")
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serialize_equal(tpe.SIntType(width.IntWidth(32)), "SInt<32>")
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def test_vector_type():
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vt = tpe.VectorType(tpe.UIntType(width.UnknownWidth()), 16)
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serialize_equal(vt, "UInt[16]")
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