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PyHCL
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firrtl_ir: add uint/sint test

This commit is contained in:
Gaufoo 2019-11-12 23:55:16 +08:00
parent bfd93b23c7
commit a841bedbd1
2 changed files with 13 additions and 1 deletions
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2
README.md
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@ -1,5 +1,5 @@
# Py-HCL
[![Build Status](https://travis-ci.com/scutdig/pyHCL.svg?branch=master)](https://travis-ci.com/scutdig/pyHCL)
[![Build Status](https://travis-ci.com/scutdig/py-hcl.svg?branch=master)](https://travis-ci.com/scutdig/py-hcl)
[![codecov](https://codecov.io/gh/scutdig/py-hcl/branch/master/graph/badge.svg)](https://codecov.io/gh/scutdig/py-hcl)
A Hardware Construct Language

12
tests/test_firrtl_ir/test_type.py
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@ -10,6 +10,18 @@ def test_clock_type():
serialize_equal(tpe.ClockType(), "Clock")
def test_uint_type():
serialize_equal(tpe.UIntType(width.UnknownWidth()), "UInt")
serialize_equal(tpe.UIntType(width.IntWidth(8)), "UInt<8>")
serialize_equal(tpe.UIntType(width.IntWidth(32)), "UInt<32>")
def test_sint_type():
serialize_equal(tpe.SIntType(width.UnknownWidth()), "SInt")
serialize_equal(tpe.SIntType(width.IntWidth(8)), "SInt<8>")
serialize_equal(tpe.SIntType(width.IntWidth(32)), "SInt<32>")
def test_vector_type():
vt = tpe.VectorType(tpe.UIntType(width.UnknownWidth()), 16)
serialize_equal(vt, "UInt[16]")