mirror of https://github.com/llvm/circt.git
b937bcfab0
This PR extends compreg's powerOnValue operand to be able to capture more complicated initialization such as firreg's randomized initialization or DPI calls. This change should make register initialization more modular and a step forward towards https://github.com/llvm/circt/issues/7213. While ASICs might not have explicit initial values, they are crucial for simulation and FPGA implementation. FPGA designs often require constant initial values, while simulation allows for more complex initialization using expressions like function calls `$random`, `$readmem`, and `$fopen`. seq.compreg has a (optional) powerOn operand that is lowered into inlined assignment in SV which allows users to initialize registers with user-specified values. However this representation is not sufficient for initialization with function calls. In order to represent various kinds of initialization, `seq.initial` op and `!seq.immutable` type are introduced. The `seq.initial` operation produces values with types wrapped in `!seq.immutable`. The `!seq.immutable` type wrapper prevents initial values from depending on time-variant values. Stateful operations typically require corresponding initial values with the `!seq.immutable` type. This ensures that the initial state of the operation is well-defined and independent of time-variant factors. Example Input: ```mlir %r_init, %u_init = seq.initial { %rand = sv.macro.ref.se @RANDOM() : () -> i32 %c0_i32 = hw.constant 0 : i32 seq.yield %rand, %c0_i32 : i32, i32 } : !seq.immutable<i32>, !seq.immutable<i32> %r = seq.compreg %i, %clk initial %r_init : i32 %u = seq.compreg %i, %clk initial %u_init : i32 ``` Output Verilog: ```verilog reg [31:0] r; initial r = `RANDOM; reg [31:0] u = 32'h0; ``` |
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| .. | ||
| CommandGuide | ||
| Dialects | ||
| PyCDE | ||
| includes | ||
| CMakeLists.txt | ||
| Charter.md | ||
| FormalVerification.md | ||
| GettingStarted.md | ||
| HLS.md | ||
| Passes.md | ||
| PythonBindings.md | ||
| RationaleSymbols.md | ||
| Scheduling.md | ||
| ToolsWorkarounds.md | ||
| VerilogGeneration.md | ||
| dialects.dot | ||
| dialects.drawio | ||
| doxygen-mainpage.dox | ||
| doxygen.cfg.in | ||