Hideto Ueno 97da411151 [ExportVerilog] Fix two state type emission of aggregate types (#7189) ... This PR fixes an issue that `emitAsTwoStateType` flag was not propagated for aggregate types. This PR also fixes a bug that ctypes (int/shortint etc) are used as an inner type of packed types (e.g. `int [2:0]` is invalid) according to SV spec 6.8.		2024-06-18 01:14:50 +09:00
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AffineToLoopSchedule	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
ArcToLLVM	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
CFToHandshake	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
CalyxNative	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
CalyxToFSM	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
CalyxToHW	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
CombToArith	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
CombToLLVM	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
CombToSMT	[CombToSMT] Register dependency on func (#7098)	2024-05-28 21:46:54 +02:00
ConvertToArcs	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
DCToHW	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
ExportChiselInterface	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
ExportVerilog	[ExportVerilog] Fix two state type emission of aggregate types (#7189)	2024-06-18 01:14:50 +09:00
FIRRTLToHW	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
FSMToSV	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
HWArithToHW	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
HWToBTOR2	[Verif] Add PrepareForFormal pass (#7175)	2024-06-14 12:07:06 -07:00
HWToLLHD	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
HWToLLVM	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
HWToSMT	Bump LLVM	2024-05-22 13:24:29 -07:00
HWToSV	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
HWToSystemC	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
HandshakeToDC	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
HandshakeToHW	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
ImportVerilog	[ImportVerilog][MooreToCore]Lower moore.namedConstant to hw.param.value (#7122)	2024-06-14 09:22:46 +08:00
LLHDToLLVM	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
LTLToCore	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
LoopScheduleToCalyx	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
MooreToCore	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
PipelineToHW	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
SCFToCalyx	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
SMTToZ3LLVM	[SMT] Add quantifier support to LLVM lowering (#6973)	2024-05-02 10:09:14 +02:00
SeqToSV	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
SimToSV	[SimToSV] Fix DPICall lowering to use `replaceOp` (#7192)	2024-06-17 19:44:20 +09:00
VerifToSMT	[SMT] Add function application operation, function and uninterpreted sort types (#6847)	2024-03-22 17:13:18 +01:00
VerifToSV	[NFCI][Conversion] Refactor TableGen Pass includes (#7174)	2024-06-14 16:37:29 +02:00
CMakeLists.txt	[LTL to Core] Add lowering for AssertProperty operations (#6974)	2024-05-02 12:57:52 -07:00